The promise of high-level synthesis (HLS) is a powerful one: the ability to generate production-quality register transfer level (RTL) implementations from high-level specification...
High-level synthesis blue book - Michael Fingeroff - Calypto
The promise of high-level synthesis (HLS) is a powerful one: the ability to generate production-quality register transfer level (RTL) implementations from high-level specification. In other words, HLS automates an otherwise manual process, eliminating the source of many design errors and accelerating a very long and iterative part of the development cycle.
To read the interview with Mike Fingeroff, see the first part of this book excerpt
To get a copy of this book click here
Making the case for high-level synthesis
General C++ Style
Bit accurate data types
Fundamentals of high-level synthesisScheduling of I/O and memories – excerptedSequential and combinational hardware – excerpted this week
Advanced hierarchical design
Chapter 5 Scheduling of I/O and memories
to loop pipelining and loop unrolling, the way in which IO and memory
accesses are coded in a design can have a significant impact on both
area and performance. IO and memory accesses tend to be the bottleneck
in a system and they can potentially limit the ability to pipeline a
design, or negate the benefits gained from loop unrolling. In the worst
case using bad style when coding IO or memories prevents scheduling a
There are two primary ways for passing IO into and out
of a design, pass by value and pass by pointer or reference, which
includes arrays. Using one over the other can lead to very different
Chapter contents (highlighted subject will be provided)
Conditional IO - new this week
Chapter 6 Sequential and combinational hardware
The previous chapters provided a good introduction to the principles behind high-level synthesis and the use of bit-accurate data types. The basics of scheduling and loop optimizations were illustrated using concepts familiar to RTL designers, such as hardware diagrams, state machines, and timing diagrams. The next logical step is to take this foundation and apply it to some real world hardware examples. In a similar fashion to most RTL design guides, this chapter presents many of the basic hardware structures that RTL designers are familiar with, and shows how to code them using synthesizable C++. Unlike the examples of previous chapters, which focused primarily on a C-like coding style, class-based/object oriented C++ is introduced, including templates and recursion. As this chapter progresses the reader can begin to see the true power of hardware design using C++. The hardware examples presented in this chapter are all depicted as sequential circuits. This is because it is assumed that each example is synthesized as the top-level design. When used in the context of a larger design these circuits may be sequential or combinational based on the clock frequency and how the design is scheduled. True combinational components can also be synthesized by using explicit directives in the C++ synthesis tool.
Chapter contents (highlighted subjects will be provided in excerpts)
Helper Classes for Design Reuse
Priority Search Hardware
Lookup Tables (LUT)
To get a copy of this book click here
Other book excerpts:
Power Integrity Modeling and Design for Semiconductors and Systems
Introduction to Open Core Protocol The art of hardware architecture Brian Bailey
– keeping you covered
If you found this article to be of interest, visit EDA Designline
where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here
to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).