LVS debug of today's complex designs is challenging and time-consuming, but reducing LVS debug time while continuing to provide reliable, high-performance designs is a requirement for chip designers who want to meet their tight tapeout deadlines and satisfy customers.
found in the extraction process are often just text conflicts that
occur due to different text -names being present on the same net. With
traditional LVS technology, when shorts are identified after an LVS run,
the errors must be corrected and the extraction process run after each
error correction, each time lengthening the total time required for the
LVS process to achieve an LVS-clean result.
between extraction errors and true comparison errors, advanced LVS
debugging techniques enable designers to identify and correct these
errors before moving on to the debugging of the true comparison errors.
In our example, once Calibre nmLVS has run the LVS process and generated
a shorts database, the results are displayed in Calibre RVE, a results
viewing tool. The first thing you notice is that extraction errors are
now separated from the comparison errors (Figure 1). This separation
enables designers to analyze and correct errors created in the
extraction netlist, such as shorts created by text conflicts.
Figure 1: Calibre RVE interface with extraction and comparison results displayed separately.
a Calibre RVE feature called Interactive Short Isolation (ISI),
designers can now fix multiple top-level power-ground shorts without
having to run the extraction process after each error correction. With
ISI, designers identify the polygons constituting a short. They then
highlight the shorted path in Calibre DesignRev (a layout viewing tool),
step through the polygons, and assign net name text (VDD or VSS) to
each of the polygons, based on their knowledge of the design layout
(Figure 2). In this way, they can quickly and progressively get to the
location of a texted short.
2: Identification of polygons constituting a shorted path between Power
& Ground Nets in pllclk cell. The shorted path is then highlighted
in the design viewing environment, enabling designers to assign net
names to the polygons constituting the shorted path.
designers locate the shorted polygon, they can virtually remove this
polygon from the shorts database and run ISI to see if the short is
corrected. During ISI, Calibre nmLVS does not launch the extraction
process. Instead, it utilizes the extraction information present in the
shorts database, which allows ISI runs to generate results very quickly.
This speed allows designers to conduct a what-if analysis on their
designs to rapidly deduce the optimum solution to fix the shorts.
Designers can quickly make a few changes in the design to fix the short,
run ISI, and see the results of those changes. At any stage of the
analysis, designers can revert back to the original shorts database
generated from the Calibre nmLVS run.
If the change made to the
shorts database fixes the short, then Calibre RVE displays the next
shorted path between the two nets (Figure 3) and the process is repeated
until no additional shorts are found (Figure 4).
3: The next shorted path between power-ground nets in pllclk cell is
shown in Calibre RVE and highlighted in Calibre DesignRev.
Figure 4: Results of Interactive Short Isolation when no other short is present between the power–ground nets in cell pllclk.
course, at this point, the changes made to fix the shorts are virtual
changes to the shorts database, not actual changes made in the design.
To actually fix the shorts, the designer must make permanent changes in
the design environment to remove the shorted polygons.