In its quest to expand into new markets, ARM announced two new intellectual property blocks that will enable it to better target networking and communications applications. ARM announced the introduction to the CoreLink CCN-504 network IP (essentially an on-die network) and the CoreLink DMC-520 dynamic memory controller.
The CoreLink CCN-502 offers approximately a Terabit per second performance; features a 128-bit internal bus, a snoop filter, up to 16MB of shared L3 cache, and dual memory channels for connection to CoreLink DMC-520 memory controllers; and support for up to 16 32-bit (ARM Cortex-A15) or 64-bit (ARM v8) cores and up to 18 AMBA I/O interfaces.
ARM claims that the architecture also features extensive clock gating allowing for lower power than competing architectures at comparable performance. The CoreLink CCN-520 memory controller, the fifth memory controller available from ARM, offers 25.6 GB/s per channel performance with ECC, integrated QoS regulation, and TustZone functionality with x72 DDR3, DDR3L and DDR4 DRAM.
The new IP offerings are part of a bigger picture to expand the ARM IP portfolio making it more attractive for other applications and more competitive with other process architectures. In this case, the applications are the outer edge of the communications network and storage.
While Intel is also targeting many of these applications with the X86 architecture and many of the IP acquisitions the company has initiated or completed over the past year, the current incumbents are often other RISC architectures and custom ASICs, which are architectures we at TIRIAS Research expect the ARM architecture to displace before going head-to-head with the X86 in servers.
Just as important as the new IP, however, is the ecosystem support that is adopting it. ARM has already received support from a laundry list of SoC partners, including Broadcom, Cavium, Freescale, Huawei, LSI, Mindspeed and TI, as well as others that are unannounced. It is this broad ecosystem support that really makes the ARM architecture attractive for future server applications.
The server segment has always maintained the widest array of processors architectures because the requirements of servers vary greatly by the applications and functions being performed. The ARM architecture will not only offer a wide range of vendors to choose from, it will also offer a broad range of SoCs that vary by vendor but are still consistent in the base architecture. This will still not offer the software compatibility of the X86 architecture, but the tradeoff in flexibility, ecosystem support, power and/or specific performance metrics may be worth the added software overhead.
As indicated in earlier articles, the true battle between the ARM and X86 architectures is unlikely to occur until the 2014/2015 timeframe, but it’s clear that both sides are gearing up for that battle and taking out the smaller competition in the interim.
Jim McGregor TIRIAS Research Founder/Principal Analyst
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.