Recently, a gossip rag that will remain unnamed tried to make up a story about how Michael (Mac) McNamara of Cadence had demanded that he be given control of their C-to-Silicon tool and when he failed, left the company. That so called reporter attempted to reach his competitors for comments, but I talked to Michael to find out what was really happening. No gossip – just facts, but I guess some people love the shock and horror stories. So be it – you just keep believing him.
Brian: So, Mac is anything in that article true?
Mac: I am no longer at Cadence. That is true. It is also true that I am running a new company, known as Adapt IP which develops IP using the TLM Design and Verification Methodology my team at Cadence published in 2010.
To address the rest of the rumors, let me say this - I worked at Cadence for seven years, as the VP & GM of System Level Design, and during those years created two different business units from scratch (C-to-Silicon Compiler and Virtual Systems Platform). For each business unit, I created a small team to craft the business plan and pitch it to executive staff, and got each funded. Then for each I recruited and managed the staff to build the tools and methodology, and worked with sales to win the early customers and take the product to the mainstream. Both business units are going strong and all indications are that Cadence continues to believe and invest in them. Perhaps one reason Mike Fister chose me for this task was that before joining Cadence I did many of these same tasks for traditional EDA startups as a part of the founding teams of Chronologic and SureFire Verification, and as a member of executive staff at Verisity Design.
There have been a number of books written about how to do a startup inside a major corporation, and basically, it is an unnatural act. Geoffrey Moore wrote a book about this challenge, called “Dealing with Darwin” and as he notes, it is not an easy task. Some major corporations, like Proctor & Gamble do this fairly well, but they are the exception. For most industries (including EDA) the easier method is to simply acknowledge the fact that the naturally occurring entrepreneurial people will create startups anyway and these will react directly to emerging customer needs. They create new technologies and prosper or fail according to the principle of survival of the fittest. The savvy major corporations in the industry can snap up the successful startups once they’ve refined the business model to achieve profitability. Those serial founders that retain the itch go off and do it again. This is a big part of the story of how EDA evolved for the past 30 years.
Brian: So, why did you leave Cadence?
Mac: Well, first, I certainly had the itch to start another company. Second, my experiences at Cadence showed me that there was an emerging innovation opportunity to apply the new TLM D&V methodology to chip design. Third, the maturity of the C-to-Silicon and Virtual System Platform products and development teams, coupled with a timely reorganization at Cadence created a fairly natural break point where I could leave these organizations in the capable hands of a new leader who could continue to grow these businesses.
Disruptive new technologies such as TLM D&V impose a switching cost on organizations. There are many companies with very efficient teams who can create RTL implementations of new protocols and algorithms, verify them, and fabricate them into the devices we all carry around with us. As Cadence’s VP for System Level Design, I was having some success in convincing the most agile of these organizations to retool their design and verification departments to capture and verify these protocols and algorithms at the TLM level, and realize both the cost savings, and the improved time-to-market. However quite a few organizations have entrenched expertise at the RTL level, and were not able to make the investment to retrain (or acquire new) staff with the needed skills. Instead these companies make incremental investments in reducing design costs (establishing off shore RTL design centers for their critical IP, and implementing a larger percentage of the rest of their SoCs using purchased IP from outside suppliers).
As one of the authors of the new methodology, I am a believer and based on my deep understanding of the costs and benefits of TLM D&V I am in the middle of building a company to be damn good at creating IP at this abstraction node, and delivering it to today’s customers as customized, verified RTL they are increasingly looking to purchase.
Brian: So, tell me about Adapt IP?
Mac: I re-joined my good friend and serial entrepreneur John Sanguinetti (we first worked together at Ardent Computer in 1988, and then at Chronologic in 1992; and he was on the board of my company SureFire Verification). In 2009, John established a company called HighIP Design, focused on applying high-level synthesis to the creation of digital IP. I liked this idea but believed that additional customer value, and IP production efficiencies could be realized by applying the complete TLM design and verification methodology.
We renamed the company Adapt-IP, recognizing that most customers interested in purchasing IP would want some customizations, and would need these verified. Adapt-IP is optimized to be efficient at making these modifications to our base implementations of standards-compliant IP, and to deliver these with a verification environment to our customers, along with devices drivers for Linux and Windows platforms.
The company has an implementation team, made up of people with expertise in taking designs expressed as a spec, or ideally as a C++ program, and refining the program to be both adaptable (so we can add/delete features) and synthesizable (so we can quickly generate RTL for the particular FPGA or ASIC flow required). The company has a verification team, who build adaptable test-benches which can be extended for new features, and the particulars of the required implementation fabric. Finally the company has a set of Domain Experts, who bring their knowledge of the particular area to guide the implementation team, and also to interface with customers as a resource in helping them to deploy our technology to meet their needs.
I recruited Sean Smith, an expert in applying constraint-driven verification to digital designs, to lead the verification team. Sean was an early user of Verisity’s Specman methodology at Cisco, and also brought IP design and EDA experience from Denali to my team. Phil Tharp is our domain expert for USB, and leads the implementation team.
Brian: Tell me more about Vreelin, and your company’s USB expertise
Mac: Vreelin has been in the business of developing integrated circuit IP and device drivers on contract for companies including IBM, Conexant and FWB, making devices including USB V.90 modem, USB ADSL modem, as well as supplying USB 2.0 Highspeed FPGA cores for many customer-specific projects over the past two decades. We acquired Vreelin.
Phil Tharp got interested in applying high-level synthesis to USB design a number of years ago, and successfully built a USB 2.0 core using this technology. Here at Adapt-IP, Phil has built a USB 3.0 core (device, host, hub and embedded host), and it is being tested with our customers and prospects.
Brian: Tell me about your other cores and your development plans
Mac: Our product development focus is on what I call “High Delta IP” – areas of design that are under active revision, and also in heavy use in consumer devices. This ‘active revision’ aspect has been the bane of existence for IP design. Using traditional design methods, an IP company needed each of their designs to be ‘hot’ for a few years in order to recapture their large development costs. Because we’ve designed our company to be good at adapting IP to fit customer’s needs, we can focus on these high-value targets.
Video is a high delta area and H.265 is the next video compression/decompression standard, extending the current H.264 to deliver the higher compression needed for the larger pixel counts of the bigger TVs and tablets. This is one of our development areas.
Forward error correction is yet another high delta technology, and LTE is everyone’s next IP in this area. We are in the midst of developing this technology.
Brian: Are you using the Forte high-level synthesis tools?
Mac: Vreelin and HighIP were using Forte, and so we do have licenses for Cynthesizer and we are using it to implement the TLM Design and Verification Methodology. It works and so do the Cadence and Calypto tools. Adapt-IP is talking with all of the suppliers of technology for this new design style. But it is not about the tools – our focus is on adapting standards-compliant IP to fit our customer’s needs and delivering the design, verification and device drivers to them.
Brian: Any customer announcements yet?
Mac: Vreelin and HighIP had a number of existing customers and they are interested in continuing to work with us.
Anyone who has read the Cadence book “TLM-driven Design and Verification” will know what we are doing. We are building key foundational IP at the TLM abstraction and verifying it. We are then engaging with prospects to understand their particular design needs (features & technology nodes) and customizing the foundational IP to directly fulfill their requirements. Unlike other IP companies, we provide the customized hardware, software and the verification hooks needed to efficiently incorporate our IP into our customer’s products. Many of the other IP companies claim they are doing this but if you talk with their users you will find the reality is the software and test-benches they deliver seem to be afterthoughts, and are not meeting the end customer needs. We intend to raise the standard.
Brian: Thanks Mac, and good luck with the new business model! I say that someone else needs to be sent to the funny farm.
Brian Bailey – keeping you covered
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