I will be the first to say that there is still a lot of room for improvements with 3D ICs and the levels of automation that go into their design, but this week it has become clear that this can no longer be considered as just an emerging technology used by a few progressive companies. The first piece of evidence supporting this was the announcements made by TSMC this week about the first Chip on Wafer on Substrate (CoWoS) test vehicle using JEDEC Solid State Technology Association’s Wide I/O mobile DRAM interface., an advancement that will pave the way for mixed logic and memory chips. Cadence, Mentor and Synopsys were quick to talk about their product and IP support for this.
Then we have data from Research and Markets who claim that 3D using TSVs will be 9% of the total market by 2017, growing 10 times faster than the global semiconductor industry. Today most of those chips are being used to bring in CMOS image sensors, Ambient light sensors, Power Amplifiers, RF and inertial MEMS – but even that represented a $2.7B market last year and by 2017 will be $40B. They also say that 3DICs which use TSV 'via middle' for memory and logic IC stacking is expected to grow the fastest in wafers as well as in overall value.Brian Bailey
– keeping you covered
If you found this article to be of interest, visit EDA Designline
where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here
to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).