TSMC announced that it has taped out the first CoWoS™ (Chip on
Wafer on Substrate) test vehicle using JEDEC Solid State Technology
Association’s Wide I/O mobile DRAM interface. The milestone demonstrates
the industry’s system integration trend to achieve increased bandwidth,
higher performance and superior energy efficiency. This new generation
of TSMC’s CoWoS™ test vehicles added a silicon proof point demonstrating
the integration of a logic SoC chip and DRAM into a single module using
the Wide I/O interface.
Mentor Graphics announced that IC
physical design, verification, thermal analysis and test design tools
that have been selected for TSMC’s new CoWoS™ Reference Flow.
that it is delivering a comprehensive 3D-IC design solution that is
included in TSMC's CoWoS Reference Flow. Synopsys has released enhanced
versions of its Galaxy Implementation Platform tools for physical
implementation, parasitic extraction, physical verification and timing
Cadence says that TSMC has validated Cadence
3D-IC technology for its CoWoS Reference Flow with the development of a
CoWoS test vehicle that includes an SoC with Cadence Wide I/O memory
controller and PHY IP.
Cadence also says that its full
suite of 3D-IC technologies were deployed by Taiwan's Industrial
Technology Research Institute (ITRI) to develop a 3D-IC chip. The test
chip is a wide I/O memory stack with through-silicon vias (TSVs).
announced 20-nanometer (nm) process technology support for the TSMC
20nm Reference flow. This includes Synopsys® Galaxy™ Implementation
Platform support for the latest TSMC 20nm design rules and models.
supports TSMC 20nm process technology. MunEDA will also be providing
several circuit tutorial cases using the MunEDA WiCkeDTM analysis and
sizing environment targeting TSMC 20nm process technology. The tutorial
cases include a high-sigma worst-case analysis of a memory SRAM bitcell
as well as numerical sizing of a high-speed I/O level shifter.
Berkeley Design Automation
has announced that TSMC has incorporated the Analog FastSPICE Platform
in its Custom Design Reference Flow for 20nm Device Noise Analysis and
Circuit-Specific Process Corners.
Mentor Graphics has
announced new capabilities to complement TSMC’s 20nm manufacturing
processes. Enhancements to support both digital and analog/mixed signal
20nm reference flows include new features in the Pyxis™ IC Station
platform, the Eldo fast SPICE simulation products, the Olympus-SoC™
place and route system, the Calibre® nmDRC™, Calibre RealTime, Calibre
PERC™ and Calibre xACT 3D solutions, and the Tessent® silicon test
SpringSoft and Mentor Graphics jointly announced that
the Laker™-Calibre®RealTime custom layout flow with signoff-quality
design rule checking (DRC) in real time is selected for the TSMC Custom
Design Reference Flow.
And SpringSoft announced that the Laker3™ Custom IC Design Platform has been included in TSMC's 20-nanometer (nm) Custom Design Reference Flow.
has successfully completed a tape-out in TSMC’s 20nm manufacturing
process and the announces the availability of a Mixed Signal Design Kit
(MSDK) for this advanced node.
ATopTech has announced that Apris and Apogee, the company’s place
and route solution, are included in TSMC’S 20nm Reference Flow.
Brian Bailey – keeping you covered
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