Building on its announcement with AMD, ARM unveiled the details of the 64-bit v8 architecture. The first v8 processor cores will include the Cortex-A57 and Cortex-A53 in a follow-up to the big-little strategy introduced with the A15/A7 generation just now entering production.
The A57 will be the performance optimized core and the A53 with be the power optimized core. Both new cores are designed to work in conjunction with the CoreLink network and memory controllers introduced recently.
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The new cores build on the architecture enhancements of the A15/A7 with the same pipeline structures. ARM anticipates a 5x performance over quad-core Cortex-A9 (32-bit) processors shipping today at similar die sizes and power consumption. The increase in performance is a result of moving from the 32/28-nm process node to 22-nm plus improved branch prediction, prefetching, and cache throughput.
The new architecture still features up to four cores per cluster, but increases the number of clusters to four or more, as well as adding additional registers, larger buffers and improved cache coherency and error correction. The new architectures will also be able to support both the new v8 64-bit instruction set and the v7 32-instruction set.
As with previous generations, new products are likely two years away. So far, the announced processor partners for the new architecture include AMD, Calxeda, Broadcom, HiSilicon, Samsung and STMicroelectronics. Noticeably missing from the list of processor vendors is Nvidia and its project Denver targeting server applications.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.