Layout merging is a routine practice in chip design. When this happens, cells from different layout files may have the same name. The choice of how to process these duplicate names depends on the situation.
To understand the ability of these new automated file merging
techniques, let’s take a closer look at one specific option available in
the Calibre DESIGNrev filemerge process—–smartdiff. By default, the Calibre DESIGNrev filemerge process compares cells by name alone. Using –smartdiff, the design team instructs the Calibre DESIGNrev tool to compare the contents of cells with identical names. With –smartdiff,
once a name conflict is discovered, the filemerge process performs an
XOR on the cell contents of the cells with a name conflict. If the name,
contents, and properties match, the cell in the incoming file is
ignored. If the names match, but the contents or properties differ, the
cell in the incoming file is given whatever treatment is specified by
the “blind” merge modes -append|-overwrite|-rename|-force-rename.
> calibredrv –a layout filemerge –smartdiff \
-in my_design.gds –in block.gds
-out my_design_with_block.gds –rename
Figure 3 shows the same example from Figure 1 after running a Calibre DESIGNrev filemerge with –smartdiff
post-processing option –topcell to clean up the result. Cell E is left
as is, since it was already updated. Placeholder Cells F and G are
replaced by the updated IP library cells. The IP library Cell C was
renamed to C_WB1 before being added to the layout, because by using –smartdiff
Calibre DESIGNrev recognized that the IP library cell C and the layout
Block C were not the same, so it then performed a rename as instructed
by the –rename
Figure 3. After running the filemerge process with –smartdiff, the layout file has been updated with the new IP cells as necessary.
Even in the case where the cell renaming requirements are simple, –smartdiff
can make the output file more compact, with less redundant data.
automated EDA tool capabilities are emerging to help design teams
handle complicated file design tasks, such as selectively updating
library cells, or merging block and full chip layouts. Sophisticated
file merging processes can now be initiated using chip finishing
platforms, reducing time to market, ensuring accuracy, and eliminating
worrisome and tedious manual processes. As we continue our march down
the nanometer road, EDA support for these complex activities is crucial
to ensuring our forward momentum.
About the author
Tong is a Technical Marketing Engineer with Mentor Graphics, focusing
on Interactive and Integration Technology for the Calibre product line
in the Design to Silicon division. Prior to joining Mentor Graphics,
Yijun worked for Intel Corporation. He received his B. Sc. in Electrical
Engineering from Fudan University in Shanghai, China, and a M.Sc. in
Information Systems Management from Carnegie Mellon University in
Pittsburgh, PA. Yijun can be reached at email@example.com.
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