This is a consolidated listing of all of the blogs written by Mentor Graphics, that have appeared in the EDA Designline.
Consolidated listing of blog from the folks at Mentor Graphics.
Circuit reliability: Old problem? New problem? Or both?, Carey Robertson
DRC debugging challenges in AMS/custom designs at 20 nm, Srinivas Velivala
Parasitic extraction in the age of double-patterning, Carey Robertson
Rethinking communications: Automating tapeout review reporting, Yijun Tong
It is time to take SoC verification out of the lab, Richard Pugh
Chip Integration: Solving Duplicate Name Conflicts During File Merging, Yijun Tong
LVS Debug: The Good, The Bad, and The Future, Srinivas Velivala
Power domain verification: Beyond traditional DRC, LVS and ERC, Srinivas Velivala
Conquering Behemoth Designs, Andy Inness
Challenges in chip integration, Joe Davis
Interconnect Modeling at 20nm – More of the Same or Completely Different? Carey Robertson
Density Requirements at 28 nm, Joe Davis
Calibre PERC: Preventing Electrical Overstress Failures, Carey Robertson
Successful Adoption of DFM, Mark Redford - Cambridge Silicon Radio, and Jean-Marie Brunet – Mentor
Location Is Everything: Improving Performance with Interactive LDE Estimation, Ahmed F. Abo-ElHadeed, Amr Essam, Amr M.S. Tosson, Ahmed Ramadan, Mohamed Dessouky.
Critical Area Analysis and Memory Redundancy, Simon Favre
Virtual vs. Physical Prototyping, John Isaac
System Performance Analysis and Software Optimization Using a TLM Virtual Platform, by Mike Bradley and Jon McDonald
Debugging for antenna issues in copper processes, John Ferguson and Vigen Boyajyan
Design optimization of flip-chip packages integrating USB 3.0, by Rod Duzinski - Mentor, Manoj F. Nachnani - Enabling Solutions, Inc.
Evolution of manufacturing closure for advanced nodes (Part 3), Ivailo Nedelchev, Sudhakar Jilla
Attofarad accuracy for high-performance memory design, Claudia Relyea
Evolution of manufacturing closure for advanced nodes (Part 2), Ivailo Nedelchev, Sudhakar Jilla
The War Is Over: Using C++ and System C in One Tool, One Flow, Thomas Bollaert and Mike Fingeroff
Ease production at 65nm with DFM, Jean-Marie Brunet - Mentor, Mark Redford, Colin Thomas and Mark Scoones - Cambridge Silicon Radio
EDA focus shifts to system level design, Walden Rhines
Evolution of manufacturing closure for advanced nodes (Part 1), Ivailo Nedelchev, Sudhakar Jilla
How to instrument your design with simple SystemVerilog assertions, Ping Yeung
Wither Interoperability, the myth of the grand unifying EDA database, Linda Fosler
Brian Bailey – keeping you covered
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