I asked all the companies in my contact list (let me know if you didn’t receive the call so we can make sure you are included next time) to talk about the most significant developments that they had seen in 2012. I also asked for their predictions for 2013 and they will come later. It should not be too surprising that most companies wanted to talk about their significant advances for the year and it is interesting to see what they believe were their crowing achievements. For some, the advances were business in nature, such as increased revenues or company size, for others it was more technical in nature, such as new capabilities they were offering.
I received input from 23 companies and will organize that feedback into several categories: general industry observations and trends, business success and expansions, verification, design – including analog mixed-signal, semiconductor and IP and a few miscellaneous tools and items.
Today I will comments that talk about general industry observations, trends and surprises in 2012. They are in no particular order.
Mike Gianfagna - Vice President of Corporate Marketing, Atrenta Inc.
FinFETs and 2.5/3D ICs inched closer to the mainstream. Both of these advances will have a big impact on design methodology and the economics of the semiconductor industry - hopefully in a positive way.
It looks like Moore's Law really is slowing down. Some have coined the term "Moore Stress". The idea is that the cost of transistors at advanced nodes is actually going up, and not down for the first time. Things like 3D ICs will help address the problem, but the issue is bigger than that. We've been talking about the productivity gap between technology advances and design advances for years. This "Moore Stress" trend suggests it's finally going to hit the industry hard. It's time for substantial new innovation in EDA, or whatever the EDA business evolves into.
Bill Neifert - Chief Technology Officer, Carbon Design Systems
The industry has come a long way in its acceptance and adoption of virtual prototypes. That wasn’t a sure thing just a few years ago.
Dr. Raik Brinkmann - President and Chief Executive Officer - OneSpin Solutions
Design teams are adopting deep formal or the ability of formal verification tools to take on a higher level of technology. That is, the tools are able to verify the complexity of functions, something that few formal verification tool providers are able to offer. 2012 is the year we’re seeing more widespread adoption.
Adnan Hamid - Chief Executive Officer, Breker Verification Systems
The biggest surprise of 2012 was the surprise many SoC design teams received when they realized stitch and ship doesn’t work. This optimistic verification process will sink them every time because they’ve failed to exercise a wide range of functional scenarios. A common misperception is that the SoC will work as intended if the IP blocks on the chip have been well verified. In fact, scenarios that represent user applications and measure performance can only be run at the full-chip level.
Oz Levia - Vice President of Marketing and Business Development and Corporate Counsel, Jasper Design Automation
Industry wide, the biggest news was the continued consolidation in EDA, with Synopsys leading a charge that started in 2009. This trend, combined with the emergence of a relatively small number of new EDA companies, has resulted in an industry that is now more stable, but less diverse.
The biggest surprise was that there has been no big surprise. After working through the downturn of 2009-2011, a return to “regular” growth and the familiar business cycle is welcome.
Michiel Ligthart - President and Chief Operating Officer - Verific Design Automation
At first thought, building your own RTL tools sounds like a preposterous idea. Why would anyone do that in a world where for each semiconductor design problem at least three different EDA tools vie for your attention and your budget? Not to mention the fact that it takes a lot of work to build a SystemVerilog synthesis tool, a VHDL simulator, or a mixed-language power analyzer.
Here’s a surprise. In reality, it is not uncommon for semiconductor design teams to do exactly that. At Verific Design Automation, we noticed that in 2012. Verific’s parsers are used by many well-known EDA and FPGA companies. The addition of Perl APIs made them more accessible to a wider audience.
Our SystemVerilog and VHDL parsers are in high demand among the semiconductor crowd, especially since we introduced our Perl APIs in the second half of 2011. Verific’s parsers are used primarily with one-of-a-kind steps in a semiconductor design flow for which no off-the-shelf EDA tools are available. For instance, companies often find a need to adjust their semiconductor IP blocks, provide a company specific test insertion strategy, or maybe need an easy way to peruse a design for linting purposes.
Whatever the final purpose, it is engineering ingenuity at its best.
Mike Santarini - Publisher of Xilinx’s Xcell Journal
It’s quite surprising how quickly the rest of the industry is starting to actively target 3D ICs for future projects. It’s nice to see that the EDA industry seems to be revving up flows and methodologies to support it. A huge facilitator of this is of course TSMCs efforts to support the manufacturing, packaging and testing of the 3D IC technologies. Xilinx being first to this market with 3D ICs has given us a sizeable competitive advantage—a generation ahead advantage at 28nm that we can learn from and maintain as we move into 20nm.
Dr. Zhihong Liu - Executive Chairman, ProPlus Design Solutions
Yield is a huge problem that is only now getting the attention it deserves. The surprise is that it took so long, though 2012 may be the year when the electronics industry recognized the importance of a design for yield (DFY), also known as managing process variations or variation-aware design, strategy. At 45nm and lower geometries including 28nm, yield is all but a crisis for process development engineers and circuit designers.
Bob Smith - Senior Vice President of Marketing, Uniquify Inc.
SoC designers and systems companies have begun to realize the value of employing “variation-aware” IP. Uniquify started this trend by extending our patented self-calibrating logic IP for double data rate (DDR) memory subsystems to solve dynamic variation problems during system operation.
Dynamic Self-Calibrating Logic (DSCL) provides real-time calibration of the memory subsystem to accommodate dynamic variations in the system operating environment. It allows this timing calibration to be applied during system operation and field reliability, critical to enhancing system yield and maintaining DDR memory system performance as temperature and supply voltages fluctuate during system operation.
Rick Stanton - Director of ENOVIA Strategy for Semiconductor and ALM Experiences, Dassault Systèmes
I was most surprised by the rate of M&A in the industry. I had expected growth in M&A, particularly for semiconductor companies that realized external acquisitions around key technology areas were necessary to complement the organic investments they were making. But there was more investment by these companies in aggressively pursuing acquisitions than I had expected.
In the EDA area, I was also pleasantly surprised by the amount of activity by Synopsys. What a year!
Linh Hong - Vice President of Sales & Marketing, Kilopass Technology Inc.
Driving the need for an antifuse alternative form of memory is the proliferation of wireless monitoring devices and digital wallets, creating a new category of battery-powered SoC designs. With embedded processing capability and wireless connectivity, these SoCs demand months or years of operation without recharge or battery swap and enhanced security requirements from its embedded memory subsystem.
Brett Cline - Vice President of Marketing and Sales, Forte Design Systems
2012 may be HLS’ breakout year. While design teams around the world have been using Forte’s high-level synthesis for more than a decade, mainstream users seem to have aggressively adopted it in 2012. Design teams have utilized SystemC HLS for large, critical portions of their designs because implementation time is greatly reduced, results are better than hand-coded register transfer level (RTL), and, ultimately, designs are far more reusable than with hand-coded RTL.
What’s interesting, though, is that the target application space continues to grow and now ranges from solid-state disk (SSD) controllers to image processing to graphics processing units (GPUs). High-level synthesis is being used across the board to help teams deliver better designs more quickly.
Chi-Ping Hsu, Senior VP, R&D, Silicon Realization Group, Cadence Design Systems, Inc.
Major structural shifts are occurring within the electronics industry. The move towards consolidated vertical segments will have profound strategic implications for years to come. Realignments like Google buying Motorola and Apple buying IC design houses will have ripple effects that wash over some companies like a tidal wave.
EUV missed another window of opportunity for deployment. New projections are saying that the window for the 10nm node may be missed as well, and that the 7nm node may be the first realistic opportunity for broad deployment of EUV.
Perhaps the biggest surprise of the year is the accelerated move to 16nm/14nm FinFET technology by the foundries. This transition is coming at a time when many people still are questioning whether 20nm is “too leading edge” for most applications.
Andreas Veneris - Chief Executive Officer, Vennsa Technologies
Year 2012 was a pivotal year for EDA, not so much for technology but because of the rapid consolidation under way. To many, it’s a surprise, though this corporate shuffling was a culmination of the maturity that the industry reached after three decades of solid, fast-growing operations. It was incubated by business practices of the 2000s and the global economic downturn in 2008-09 provided the opportunity. The recent events will set the tone in the industry for decades to come. This consolidation will drive organic growth and will strengthen the position of EDA in the semiconductor market. It will also inevitably impact start-up companies. Since most innovation in the EDA ecosystem is traditionally created within a start-up environment, large vendors will need to foster and invest for the well-being of young companies.
Over the past years, we have seen a steady shift in market demands from PCs to mobile devices such as smartphones and tablets. Though the “Death of PC” may be pre-mature or overstated, there is no doubt that the mobile market will continue to grow at a phenomenal rate. What’s interesting is that the growth in the mobile market has a direct impact on mobile traffic demand, which is expected to increase ten-fold over the next five years. This growth in mobile traffic is driving the need for rapid collection and dissemination of data via cloud computing, to seamlessly deliver on-demand self-service, network access, location-independent resource pooling, and pay-per-use capabilities. The proliferation of smart mobile devices and the IT infrastructure to support their communication is enabling the “Internet of Things (IoT)” and creating opportunities for killer application developments that take advantage of the mobility of today’s compute interfaces. The semiconductor industry is also benefiting from this disruptive force with increased demand for chips that find their way into these killer applications, and demonstrated by the growth in design starts over the past year.
Designing chips that fuel smart mobile electronics requires managing the delicate balance between performance and power. Even though power management has been the most talked about topic of the past few years, in the end performance requirements tend to supersede power management needs. However, this year we saw a shift in this balance from our customers. A key contributor to this shift (aside from the need for longer battery life, efficient energy footprint, lower power cost, etc.), is the impact that power has on thermal management. The temperature of a handheld device must be comfortable for human hands, while ICs that do not properly manage thermal affects can result in lower performance systems. Thermal management challenges become further exasperated as designs move toward more advanced process nodes and three-dimensional integrated circuit (3D-IC) architectures.
Brian Bailey – keeping you covered
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