A few weeks ago I was working with Trent McConaghy of Solido Design Automation on a paper for the EDA Designline “High-yield, high-performance memory design”. Not only was that a very popular article, but I also found out that Trent and his team had recently published a book on the subject titled “Variation-Aware Design of Custom Integrated Circuits: A Hands-on Field Guide”. This is the book review. You can find an excerpt of the book over on EDN.
As design geometries get smaller, and as we approach small numbers of electrons or atoms making up the active aspects of a device, impurities and random variations have a much greater impact than they did with the larger geometries where the variations represented much smaller percentage changes. Because of this it would be easy to start adding in greater tolerances or overdesign in order to ensure adequate yield, but the semiconductor market is highly competitive and this would lead to the creation of inferior products. Instead, better ways have to be found to reduce the uncertainty. That is the focus of this book and the associated tools that have been created by Solido.
The book starts with a forward from Jim Hogan, a well-known venture capitalist in the EDA space and an investor in Solido. In the forward he says “The use of commercial foundries […] makes it even more difficult to differentiate competitively. Performance hits are unacceptable, because all semiconductor companies are using the same foundries trying to produce competitive chips. In turn, yield hits are unacceptable for high volume applications since costs quickly skyrocket.”
Chapter 1 Introduction: Variation effects, variation-aware flows
This chapter looks at the reasons why variation happen and the various levels at which they can be grouped, such as environmental, global variations and local variations. It discusses the cause of them, and how things such as ElectroMigration can impact chips over time. It also looks at the flows that are in place today to deal with these variations and proposes a new flow that can handle them in a more efficient manner.
It is available as an excerpt over on EDN.
Chapter 2 Fast PVT Verification and Design: Efficiently managing process-voltage-temperature corners
This chapter looks at the global variations lumped as process, voltage and temperature or PVT. It defines the typical corners such as FF and SS and the typical number of corners in a design. It says “With modern process nodes, many more process corners are often needed to properly bracket process variations across different device types. Here “to bracket” means to find two corners for each spec, one that returns the maximum value and another that returns the minimum value of the respective performance output. Furthermore, transistors are smaller, performance margins are smaller, voltages are lower, and there may be multiple supply voltages. TO bracket these variations, more variables with more values per variable are needed.”
After reviewing various design flows to handle PVT variations, and comparing them on accuracy and speed, it looks at algorithms to implement a fast PVT method. It is utilizes a global optimization approach and solves it with a model-building optimization. This uses Gaussian Process Models and benchmark results are provided. A folded-cascode amplifier with gain boosting is used to analyze the results.
I like that at the end of this chapter there are two appendices that go into more detail about the algorithms. Most people will not need to understand these and providing them at the end makes the main chapter body a lot more readable.