Mike Santarini - Publisher of Xilinx’s Xcell Journal
four year development effort, Xilinx released in April a completely new
design environment called Vivado. The suite’s capacity, performance and
quality of results facilitate modern IP- and system-centric design
methodologies. It has also allowed Xilinx to field a design suite that
will scale for the coming design challenges of 20nm and beyond. One
particular highlight of the Vivado Design Suite is the tool’s ESL
capability, Vivado HLS, which will allow design teams to start projects
in C. In introducing this tool, we believe we are helping bring ESL to
the mass market to help engineers in turn bring innovations to market
Chi-Ping Hsu, Senior VP, R&D, Silicon Realization Group, Cadence Design Systems, Inc.
year we unveiled the results of a very significant multi-year R&D
program that developed support for 20nm and FinFET process technology
across our custom, analog, digital, and signoff solutions. Our
collaboration with TSMC and ARM assured a depth and breadth of
understanding that delivered design solutions capable of realizing the
full potential of the new process nodes, libraries, and IP.
increasing popularity of OpenAccess is another key milestone for 2012.
The technology that Cadence originated and contributed is now
well-established in the industry and is enabling a new generation of
methodology for custom/analog design. The new capabilities built upon
OpenAccess have produced productivity gains of 30% to 50% – a huge
contribution to customer success.
“Low-power design” is now
ubiquitous. The advanced design methodologies pioneered by Cadence have
found their way into use in the most advanced-node designs in 2012. But
they also help revitalize products at 130nm and above. Energy efficient
design goals are more achievable than ever before thanks to the
holistic approach taken in our solution offering.
Dr. Jason Xing - Vice President of Engineering, ICScape Inc.
acquisition of SpringSoft by Synopsys for the Verdi product family was a
surprise. However, it certainly presents a great opportunity for
ICScape. We are currently rolling out our sixth generation complete A/MS
tool-set for the first time to users outside of China. This will be an
excellent alternative solution, presenting an opportunity for ICScape to
become the third largest A/MS solution provider, next to Cadence and
John Chilton - senior vice president, marketing and strategic development, Synopsys
design flow has changed greatly over the past few years, including the
adoption of In-Design for physical verification, and accommodating
double patterning. A lot of these changes have emphasized the need for
increased interoperability, and this has been a great year for
interoperability. For example, the IPL initiative is now well-accepted.
Interoperable iPDK libraries are now available, so we are seeing the
beginning of competition and real innovation in the custom space. The
industry is converging around IEEE 1801 for low power. IPDKs, IEEE 1801
and verification advances such as UVM, SystemVerilog, and TLM provide a
very solid foundation of interoperable standards for design, and a lot
of that came about in 2012.
Amit Gupta - President and CEO, Solido Design
introduced four new Variation Designer products in 2012. Variation
Designer Memory+ is targeted to memory designers who must deliver
maximum yield on high performance designs. Memory+ runs the billions of
Monte Carlo samples needed for high sigma (up to 6-sigma) verification
of bitcells and sense amps, giving fast and accurate visibility into the
increasing effects of variation on design in nanometer technologies.
Memory+ uses industry-standard simulators for SPICE-accurate results,
while remaining fast enough for use in the design loop.
also introduced Variation Designer: Low Power+, which offers a typical
2x-10x productivity gain in design verification coverage across power
states, PVT corners, and layout RC corners; Standard Cell+, which can
optimize a library of cells across the increasingly significant
variation effects in nanometer technologies; and Analog+, with a 10x
average efficiency increase for PVT signoff.
introduced two major technologies over the past 12 months that address
the growing power and thermal management issues for the mobile market.
PowerArtist’s RTL Power Model (RPM™) and PowerArtist Calibrator and
Estimator (PACE™) technologies bridge the power gap from
register-transfer-language (RTL) design to physical implementation. It
accurately predicts IC power behavior at the RTL level with
consideration for how the design is physically implemented. It enables
chip power delivery network and IC package design decisions early in the
process to ensure chip power integrity sign-off for sub-20 nanometer
Apache’s RedHawk™-3DX is a fourth generation power
integrity and sign-off platform architected to address the power,
performance and price demands of low-power mobile, high-performance
computing, consumer and automotive electronics. Its core engines have
been enhanced to keep up with the Moore’s Law by delivering the capacity
to handle 1B+ gate designs. It is 20nm ready, certified by TSMC, and
provides support for multi-die 3D-IC power analysis and sign-off.
RedHawk helps analyze chip behavior, allowing cross-domain information
sharing and accurately predict the performance of the combined system.
Apache’s latest product offerings help reduce power consumption and
manage power delivery network integrity, which in turn helps reduce the
amount of generated heat and ensures reliable system operation in its
Brian Bailey – keeping you covered
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