This week, I had three segments of the 2012 retrospective. Tuesday we looked at those related to design tools and flows. Yesterday saw verification and today I conclude the series with with things related to semiconductor technology. That will wrap things up for 2012 and then it will be time to start seeing your predictions for 2013.
Mike Santarini - Publisher of Xilinx’s Xcell Journal
2012 was a year of many milestones for Xilinx. In 2012, Xilinx not only released three 28nm FPGA families but also the industry’s first 3D ICs and ARM-processor based All Programmable SoCs.
In 2012, Xilinx has expanded the possibilities of “programmability” with our heterogeneous and homogeneous 3D ICs and our Zynq-7000 SoCs. By implementing a 3D IC Stacked Silicon Interconnect (SSI) architecture stacking multiple FPGA dies (slice) side by side on top of a silicon interposer, we were able to make available today an FPGA with 2 million logic cells (20 million ASIC gates)—double the size of nearest competitor’s largest monolithic FPGA. Meanwhile, Xilinx also used the SSI architecture to create the first heterogeneous All programmable 3D IC that places FPGA dice alongside a high speed I/O die to help communications customers start designs today targeting bandwidth levels as high as 400Gbps that would not have otherwise been possible for silicon generations to come.
Another major advance in 2012 was Xilinx’s mass deployment of the Zynq-7000 All Programmable SoC. In addition to the FPGA logic in this device being programmable, the AMS block, the DSP slices, I/O, and most importantly the dual-core Cortex-A9 MPCore are also programmable—allowing Xilinx to offer a truly All Programmable device to customers to achieve new levels of system integration, reduce power and lower BoM costs.
Linh Hong - Vice President of Sales & Marketing, Kilopass Technology Inc.
Kilopass embedded non-volatile memory (NVM) IP technology called VCM (Vertical Cross-point Memory) is a major accomplishment by Kilopass’ engineering team that reduces the silicon area of an antifuse bit cell by four fold. The VCM bit cell memory technology fills an embedded NVM void not addressed by Read-only Memory (ROM), embedded flash (eFlash) or the combination of external serial-flash/EEPROM and on-chip shadow SRAM.
Today’s external serial EEPROM or serial Flash with an on-chip shadow SRAM is untenable because of power and cost constraints. The embedded flash alternative is not available at process nodes below 65nm and, even when available, adds as much as 40% to the cost of a predominantly logic SoC. The read-only memory (mask-ROM) alternative comes with the drawback of having to be configured during design and any program change requiring an expensive and lengthy design respin.
Where embedded NVM technology is cost-prohibitive or unavailable at capacities of 4Mb to 32Mb, the VCM bit cell quadruples the density of an anti-fuse NVM IP bit cell, making possible program storage. It also enables performance similar to SRAM compared to slower eNVM technologies or external flash or EEPROM chips. Brian Bailey
– keeping you covered
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