Law marches on. However, while transistors keep shrinking, atoms do
not. For 20 nanometer and smaller processes, we can basically count the
atoms: 20 nm is 200 angstroms, meaning only 200 hydrogen atoms or 80
copper atoms wide. This makes Custom 2.0 design problems atomic in
scale, where small fluctuations now have critical impact on process
variability. As a result, Moore's Law is flattening out for performance
and power; we can no longer expect the same scaling we've had for so
Given my role as Chairman of the Solido board of
directors, I spend substantial time on SPICE analysis and variation.
First, variation impacts device performance in terms of threshold
voltage. Threshold voltage has increasingly larger variance with
smaller geometries - this translates to more variance in circuit
performance, with the resulting yield loss and missed power budgets.
When we combine the shrinking transistors and the fixed atom sizes for
Custom 2.0 designs, even a few random dopant atoms out of place can
actually affect transistor performance. Devices can even end up with
negative threshold voltages, where the transistors no longer operate as
switches. This high device performance variability can make a circuit’s
performance unacceptably unpredictable.
For Custom 2.0, traditional
digital fast fast / slow slow corners are no longer adequate. We need
tools to handle statistical process variation quickly, accurately,
reliably, and that scale to industrially-sized circuits comprising
thousands of elements or more. We need a fast way to verify designs
under process variation to high statistical confidence. Process
variation has an even bigger effect on circuits where an extremely high
yield is a must-have. Such high-sigma circuits include highly replicated
blocks, such as bitcells, sense amps, and standard cells; as well as
circuits where failure is disastrous, such as parts for medical devices,
airplanes, and automobiles.
Cadence, Solido, and MunEDA are the
established players in variation analysis. Solido provides interactive
variation analysis for PVT, 3-sigma, and high-sigma statistical design,
and MunEDA provides tools geared more towards automated optimization.
Cadence includes basic variation analysis as part of their ADE
Design environments are used to setup, efficiently
run, and visualize custom IC simulation results. Cadence has a GUI
environment. Synopsys has a command-line interface, and must resolve
whether they go with Custom Designer from Synopsys, Laker from
SpringSoft, or some combination of the two. We also have Solido Design
and MunEDA - both vendors provided integrated, SPICE-neutral
environments, driving simulator usage across designers’ compute farms.
Solido and MunEDA run command-line batch modes with netlist input for
the custom digital and memory markets; they offer GUI interfaces for the
RF and Analog/Mixed Signal markets.
Companies like Solido
include variation analysis in their environments. Additionally, because
simulating-for-variation raises the number of simulation runs required,
Solido reduces the number of simulations by 10x or more by adaptively
determining what simulations are required, rather than through brute
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.