The DDR4 standard is out. The question is what does it mean to you? How do you leverage it to make a better product? Why should you migrate your design? How do you integrate compliant components in your system? How do you build compliant components? And, of course, how do you test? If you want to work with the DDR4 standard but you’re not sure where to start, learn from the experts—attend JEDEC’s DDR4 Workshop.
Scheduled for February 6-7 in Santa Clara, CA, the two-day workshop will feature sessions taught by members of the various committees involved in developing the standard. Topics include a comparison between DDR3 and DDR4, reasons to migrate, how DDR4 enhancements can ensure the integrity of bus interfaces, testing DDR4, and the shift to stacked memory.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.