After narrowly escaping the snow falling in NJ Monday morning, I made my way to DesignCon 2013 in Santa Clara in time to catch a longstanding panel: The Case of the Closed Eye starring T&M World’s own Ransom Stephens as well as Chris Loberg from Tektronix, Erick Kvamme from LSI Corp., Mike Li from Altera Corp., Greg LeCheminant from Agilent, Marty Miller from LeCroy, and Pavel Zviny from Tektronix. The bottom line from this panel is that higher data rates require better test and measurement equipment and better, more intelligent test patterns.
During the panel, Marty Miller specifically asked the question, “Is the time testing using long data patterns spent wisely?” in response to Erick’s report on how long it took him to acquire the data that underscored most of the analysis by the panel. And, Greg LeCheminant considered the questions, “what is clock recovery doing to my jitter measurements?” and “how does PLL behavior impact measurement?” He warned that it is important for test equipment manufacturers to be careful of how they do clock recovery, because long patterns, such as PRBS31, stress a test instrument’s clock recovery capability.
Tuesday morning, I attended a paper session, “Channel to Channel Crosstalk Behavior and Design Optimization for DDR4 Signaling,” which is a DesignCon Paper Award Finalist. The paper is by Xiang Li and James McCall of Intel. Unfortuantely, neither was able to attend, so James Casanova, also of Intel, gamely took over the presentation. In this work, the authors took used a motherboard with a CPU, riser card, and DIMMs to study the interfaces between the DDR4 channel and the memory buffer and the DIMMs and the memory buffer.
The area of interest was underneath the memory buffer, where the connectors were, because that’s where they looked for crosstalk. The DDR4 channel had a coupling impact on the memory buffer channel, while the memory buffer had coupling impact on the DDR4 channel. The work included creating a 3D model that represents the memory buffer interface and the DDR4 connector. It included the stripline trace from the memory buffer channel and connector via from the DDR4 backside channel. A major takeaway from this analysis was to keep to single trace routing if possible. Click here to read the rest of this article on Test and Measurement World. Janine Love is the editor-in-chief of Test and Measurement World, an EE Times sister publication.
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