At DVCon this year, I had the opportunity to sit down with Raik Brinkman, President and CEO of OneSpin Solutions.
In your submission for my 2012 retrospective series, you said that it had been a year in which you were reassessing the verification space. You also said that there had been little innovation in the area of formal verification and that design teams need tools to better observe that what they’ve done is sufficient. Can you explain this to me in a little more detail?
Brinkman: Yes, we have been reviewing our strategy in 2012 so that we can better address the market and change a little bit.
Bailey: What caused you to make this reassessment?
Brinkman: The market has changed in the past couple of years and we acknowledged this. We had to move ourselves and we recognized that the way in which verification is being done has changed. We also realized that we had to make our message simpler. So we invested in new marketing, new materials and some new products.
We have seen a shift into areas such as verifying IP blocks, IP block connectivity and other areas where you don’t need a lot of formal power. It is a lightweight use of the technology but it is something that needs to be automated. It has been done by our customers for a long time and we found that it is worth leveraging the technology.
Bailey: What is the new message?
Brinkman: The new message is about ease of use. There are several companies these days that are offering apps or solutions these days and we bundle them in with our software for no extra charge. Then there is our new observation coverage. This is push button coverage analysis for formal. This is a very important feature for people who are new to formal so that when they write assertions they get feedback about what they have achieved. So the tool can look at an assertion that you have just written and tell you that you are not going to verify anything with that.
Bailey: What is a coverage model for formal?
Brinkman: I think there is a misconception because simulation people think about coverage only from a stimulus perspective and this does makes some sense for formal as well. It enables you to see if you are over constraining the inputs. It lets you see how much of your design you can exercise. Observation coverage is the key in formal. It tells you how good your checkers are. This is a concept that is also valid for simulation but is not addressed much. If they would consider this type of usage, then it would have been included in things such as the Accellera UCIS. But they are all part of the picture and I believe they can and should be brought together.
Bailey: Is USIC something that you believe is useful as it stands?
Brinkman: It is useful because we can create interesting information and coverage metrics on the input stimulus side, such as showing them which pieces of their design are not reachable. For observation coverage it is more difficult because there is no definition in the UCIS, but this is not just a problem for us, all vendors have the same problem. I am sure that with time and work we can make them work together.
Bailey: Formal has traditionally been viewed as something that is difficult to learn and use. How has this perception changed over the years?
Brinkman: The industry is warming to formal. I think everyone understands that formal is a good technology. I think we also know the class of problems where people should be using formal such as connectivity, protocol compliance etc. We haven’t made much progress in the areas in which users are expected to write assertions. There is also a disconnect regarding when formal is not able to reach a full proof. People don’t realize that they still get a lot of benefit. You verify a lot getting to that point but the coverage metrics do not enable you to measure what you have achieved.
Bailey: Where do you find the biggest competition these days?
Brinkman: Some of the big EDA companies do not really see the value in formal and they still believe it is hard to train and educate their customers. That makes it a lower value for their time. We also see competition from the smaller companies that focus on this problem area.
Bailey: I am betting though that you biggest competitor is still simulation?
Brinkman: Yes, that is correct, although perhaps we have to ask if simulation is our competitor or our friend. We cannot make simulation the enemy, or at least we shouldn’t. We have to learn how to work with it and how they can work together. For example, if we look at SystemVerilog. It has defined two sets of constraints - one set defined in the testbench language and you can also write a property. One set (those in the testbench) is generally used for simulation and the other for formal. This is not a good idea and makes interoperability between the two landscapes more difficult and means that a double effort is required.
Bailey: You got a new round of funding last year.
Brinkman: Yes, that is correct and while I don’t want to discuss the numbers, we can say that we are self-sustaining. We have a good installed base and happy customers that are paying money. There is no rush from our investors so we have all of the time we need to develop the business.
Bailey: Thank you. We will have to leave it there.Brian Bailey
– keeping you covered
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