In 1974 Robert Dennard came up with a scaling theory that drew on Moore's Law to promise ever-faster microprocessors. If from one generation to the next the transistor length shrinks by a factor of about 0.7, the transistor budget doubles, speed goes up by 40%, total chip power remains the same, and a legion of other good things continues to be bestowed on the semiconductor industry.
Unfortunately Dennard scaling petered out at 90 nm. Clock rates stagnated and power budgets have grown at each process node. Many traditional tricks just don't work any more. For instance, shrinking transistors meant thinner gate oxide thicknesses, but once those hit 1.2 nm (about the size of five adjacent silicon atoms), tunneling created unacceptable levels of leakage. Semiconductor engineers replaced the silicon-dioxide insulator (with a dielectric constant of 3.9) with other materials like hafnium dioxide (dielectric constant = 25), to allow for somewhat thicker insulation. Voltages had to go down, but are limited by subthreshold leakages as the transistors' threshold voltage must inevitably decline. More leakage means greater power dissipation. A lot of innovative work is being done, like the use of 3D finFETs, but the Moore's manna of yore has, to a large extent, dried up.
Many application used all day contain a damn lot of tasks that can be performed in parallel. Just take an editor frame as example: rendering, spell check and syntax or grammar check can be performed in seperate threads.
The fact most application are designed with a single core in mind does not imply, the application does nit contain paralellism.
"Amdahl's Law tells us that even with an infinite number of cores, an application that is 50% parallelizable will get only a 2x speedup over a single-core design."
The key words are "an application." There are often multiple applications vying for CPU cycles, all running at the same time. So in fact, I can show how a quad-core processor shows up as only 25 percent busy, or slightly more than that, when the same app running on a single core eats up 100 percent of CPU cycles.
I've read, though, that memory buses of today show no improvement beyond what you can eek out of an 8-core processor. The problem being choreography, in essence.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.