Embedded Systems Conference
Breaking News
Blog

My ASIC+SoC reassessment

NO RATINGS
View Comments: Newest First | Oldest First | Threaded View
old account Frank Eory
User Rank
Author
re: My ASIC+SoC reassessment
old account Frank Eory   4/2/2013 11:52:38 PM
NO RATINGS
If I may muddy the waters even further, the acronymns "ASIC" and "SoC" have often been used by digital designers to describe design methodologies that are largely independent of a target "application" or one's concept of a "system." By that I mean that some of us have, for years, used what we referred to as an "ASIC methodology," which simply meant that digital logic was synthesized from RTL to standard library cells and then automatically placed & routed -- i.e., few or no custom cells of our own creation and little or no manual intervention in physical design. An "SoC methodology" was essentially a type of ASIC methodology, but included one or more large IP cores -- typically microprocessors -- that might be integrated as hard cells or might be synthesized & placed & routed using an IP provider's RTL, scripts and guidance. The concept of an analog ASIC or analog SoC of course doesn't fit either of my methodology descriptions, although some of today's very complex AMS designs might. Like I said, just muddying the waters with further abuse of those overly-used acronyms!

Flash Poll
April 2015 Cartoon Caption Contest: The Mighty Hamster
April 2015 Cartoon Caption Contest: The Mighty Hamster
Of all the exhibits in the Pre-Apocalypse Era Museum, Breek was always in awe of the unearthed details and true-to-scale reproduction of a technological creation space that the long gone humans had once inhabited.
145 comments
Like Us on Facebook

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
EE Times on Twitter
EE Times Twitter Feed