Sonics recently performed a survey about on-chip communications networks. This was conducted in a double blind manner so that they would not overly skew the results. They had 318 respondents and some interesting data showed up from the survey. Surprisingly, the survey showed that designers spend 28% of their time designing, modifying and verifying the networks on their chip. That seems like a very large amount of time especially since empirical data suggests that very little full chip verification is actually being performed, instead relying on the assumption that if all of the blocks are verified and the connectivity of the IP interconnect has been verified, then the system will operate correctly. While we all know this to be inherently false, most companies only seem to run a few system-level sanity tests.
But, back to the on-chip interconnect report. The report did confirm the types of problems that designers see with their interconnect including: meeting product specifications (45%), balancing frequency, latency and throughput (42%), integrating IP elements/sub-systems (37%) and getting timing closure (35%). The first three of these would appear to be system-level operations and so this would suggest that most of that 28% is indeed system-level verification related.
As can be expected, speeds are on the increase with a majority targeting 1 GHz or faster and multiple power domains are becoming ubiquitous.
The survey then gets to the core of the issue for Sonics. What does the future of on-chip interconnect look like? It appears that almost half of the respondents are seriously considering a network-on-chip (NoC) for their next design where a NoC is defined to be a configurable network interconnect that packetizes address/data for multicore SoCs. This compares to 33% considering a crossbar and 30% considering a multi-layer bus matrix or peripheral interconnect. When asked their organization's plans for a commercial Network-on-Chip (NoC) over the next 12 months, 11% of respondents stated that they already had a commercial NoC implemented and another 9% planned to in the next 12 months (9%).
It would appear that the desire for a NoC is dependent on the number of cores in the design. The higher the number of cores, the more problematic the interconnect problem becomes and so the more likely they are to adopt a commercial network solution.
So, what do designer’s look for in a commercial NoC? Their top 3 criteria for selecting a Network on Chip were: scalability-adaptability (49%), quality of service (38%) and system verification (38%).
For more insights, check out their info graphics that can be found here.Brian Bailey
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