In this era of ever shrinking time to market windows, for semiconductor organizations to win the race to market, they must master IP-based design, and in particular IP reuse encompassing both design and verification reuse...
In this era of ever shrinking time to market windows, for semiconductor organizations to to win the race to market, they must master IP-based design, and in particular IP reuse encompassing both design and verification reuse.
Last month, IC Manage had an independent firm run its fifth annual global blind survey of SoC and IC design professionals. Approximately half of the 372 respondents held positions in engineering, verification, project, or CAD management. Download the entire IC Manage IP Reuse survey report.
One key survey finding underscored the prevalence of IP reuse. Respondents expected an average of 68 percent of non-memory SoC and IC design content in 2013 to be reused IP, comprised of 44 percent internal IP and 24 percent third party IP. So almosts two-thirds of their non-memory IP reuse is internal IP. 32 percent of each design was expected to be new design content.
Companies today are leveraging past ideas and implementations to more rapidly deliver each new generation of technology. To achieve efficient IP reuse, team members across the enterprise - including design and verification managers, project leads, chip designers, IP owners, and verification engineers – depend on ready access to the information associated with the IP. Below are the top challenges that organizations cited for “IP reuse dependency management”.