This is a roundup of news or activities in the past few days that may be of interest to people.
Improvements to the graphical viewer and significantly faster performance are among the enhancements to ASSET® InterTech’s ScanWorks® IJTAG test tool, with which engineers are able to access, control and automate the operations of test and measurement instruments embedded in chips. ScanWorks IJTAG Test supports the new IEEE P1687 Internal JTAG (IJTAG) standard for embedded instrumentation. IJTAG gives chip designers a more effective method for debugging chip designs by standardizing the way engineers control and access the instruments they have embedded on-chip. In addition, these same embedded instruments can be re-applied later to test, validate and debug prototypes of circuit board designs and manufactured boards.
The EDA Consortium (EDAC) Market Statistics Service (MSS) today announced that the EDA industry revenue increased 4.6 percent for Q4 2012 to $1779.1 million, compared to $1700.1 million in Q4 2011. Sequential EDA revenue for Q4 2012 increased 9.8 percent compared to Q3 2012, while the four-quarters moving average, which compares the most recent four quarters to the prior four quarters, increased by 6.7 percent. Companies that were tracked employed 29,578 professionals in Q4 2012, an increase of 7.1 percent compared to the 27,623 people employed in Q4 2011, and up 2.4 percent compared to Q3 2012.
Digital Core Design is now offering an I2C bus interface soft core. It is fully compatible with Philips v3.0 specification, which means, it can operate at Standard, Fast, Fast Plus and High Speed (up to 3,4 Mb/s). Moreover, The DI2CMS allows master and slave mode, arbitration and clock synchronization, support for multi-master systems and 7-bit and 10-bit addressing formats on the I2C bus.
ProPlus Design Solutions has launched NanoSpice™, a parallel SPICE simulator for giga-scale circuit simulation. In announcing NanoSpice, ProPlus unveiled a new licensing model with simplified and practical control for parallelization, making it a cost-effective and powerful choice for advanced circuit simulations that designers typically don’t have.
GLOBALFOUNDRIES has announced a key milestone in its strategy to enable 3D stacking of chips for next-generation mobile and consumer applications. At its Fab 8 campus in Saratoga County, N.Y., the company has demonstrated its first functional 20nm silicon wafers with integrated Through-Silicon Vias (TSVs). Manufactured using a 20nm-LPM process technology, the TSV capabilities will allow customers to stack multiple chips on top of each other, providing another avenue for delivering the demanding performance, power, and bandwidth requirements of today’s electronic devices.
ARM and TSMC have announced the first tape-out of an ARM® Cortex™-A57 processor on FinFET process technology. This is the first milestone in the collaboration between ARM and TSMC to jointly optimize the 64-bit ARMv8 processor series on TSMC FinFET process technologies. The two companies cooperated in the implementation from RTL to tape-out in six months using ARM Artisan® physical IP, TSMC memory macros, and EDA technologies enabled by TSMC’s Open Innovation Platform® (OIP) design ecosystem.
Xilinx has announced a new major release of the Vivado™ Design Suite. The Vivado Design Suite 2013.1 release includes a new IP-centric design environment for accelerating the time to system integration, and a comprehensive set of libraries to accelerate C/C++ system-level design and high-level synthesis (HLS). See my blog on All Programmable Planet for more information about this.
FishTail Design Automation has announced that Japan’s Semiconductor Technology Academic Research Center (STARC) has completed a study of FishTail’s solution for merging multi-mode design constraints. This study has demonstrated that FishTail’s products drastically reduce STA runtime without any compromise on timing accuracy.
Silicon Labs says that its Ember ZigBee solutions – silicon devices, software and development tools – have achieved Golden Unit certification from the ZigBee Alliance for the newly released ZigBee IP specification. ZigBee IP is the first open standard for IPv6-based wireless mesh networking solutions, providing seamless, end-to-end Internet connectivity and a scalable architecture to control low-power devices. The new ZigBee IP specification adds network and security layers and an application framework to the IEEE 802.15.4 standard. It supports cost-effective, energy-efficient wireless mesh networks based on standard Internet protocols such as IPv6, 6LoWPAN, PANA, RPL, TCP, TLS and UDP.
Total worldwide semiconductor revenue reached $299.9 billion in 2012, down 2.6 percent from 2011, according to Gartner. With the overall semiconductor market decline, the number of vendors that declined among the top 25 outnumbered those that grew. Gartner said the top 25 semiconductor vendors' revenue declined slightly faster, at 2.8 percent, than the industry as a whole and accounted for almost the same portion of the industry's total revenue — 68.9 percent in 2012, compared with 69.0 percent in 2011.
Accellera Systems Initiative announces the formation of a new Multi-language Working Group (MLWG). The mission of the MLWG is to create a standard and functional reference for interoperability of multi-language verification environments and components. Accellera is calling for participation in the newly formed group. Accellera members and the industry at large are invited to join the standardization initiative. The MLWG will consolidate industry requirements and develop a standards-based approach to combine verification environments built in different languages. In addition, a proof-of-concept implementation is proposed to accompany the standard.Brian Bailey
– keeping you covered
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