Altera, ARM, Cadence, Chenming Hu, Cypress Semi, IC Insights, Imperas, Kathryn Kranen, Mentor, Si2 and TSMC made the lineup today. See here for their news...
This is a roundup of news or activities in the past few days that may be of interest to people.
ARM and Cadence have announced details about their collaboration to implement the first ARM® Cortex®-A57 processor on TSMC's 16nm FinFET manufacturing process. The test chip was implemented using the complete Cadence RTL-to-signoff flow, Cadence Virtuoso custom design platform, ARM Artisan® standard cell libraries and TSMC's memory macros. The 16nm process using FinFET technology presented new challenges that required significant new development in the design tools. New design rules, RC extraction for 3D transistors, increased complexity of resistance models for interconnect and vias, quantized cell libraries, library characterization that supports new transistor models and double patterning across more layers are some of the challenges that have been addressed in Cadence's custom, digital and signoff products.
At the same time Cadence announced an ongoing multi-year agreement with TSMC to develop the design infrastructure for 16-nanometer FinFET technology, targeting advanced node designs for mobile, networking, servers and FPGA applications. The deep collaboration, beginning earlier in the design process than usual, will effectively address the design challenges specific to FinFETs -- from design analysis through signoff.
The Silicon Integration Initiative (Si2) ESD (Electro-Static Discharge) Working Group of the OpenPDK Coalition has released an ESD Protection Design Flow Methodology “best practices” document for industry-wide adoption in order to promote a more consistent treatment of this important aspect of integrated circuit (IC) design. At advanced process nodes, it becomes increasingly critical to adhere to strict ESD design guidelines, because inadequate ESD protection can reduce effective yield and thus increase overall costs. This document provides comprehensive guidelines for incorporating ESD protection into IC design flows.
More than one quarter of installed wafer capacity worldwide is dedicated to producing IC devices using process geometries (or feature sizes) smaller than 40nm, according to data in IC Insights’ Global Wafer Capacity 2013. The report also shows that a surprising amount of capacity remains dedicated to mature processes with “large” features sizes. About 22% of global capacity is dedicated to the =80nm - <0.2µ segment, which includes the 90nm, 0.13µ, and 0.18µ process generations.
Kathryn Kranen, president and CEO of EDA company Jasper Design Automation Inc. has been announced as the winner of the 2013 ACE Lifetime Achievement Award. The ACE awards are given out by UBM Tech, the publisher of EE Times and EDN. Past winners include Gordon Moore, Wilf Corrigan, Irwin Jacobs and Pasquale Pistorio.
Professor Chenming Hu of the Graduate School at the University of California, Berkeley, has been announced as this year's recipient of the Phil Kaufman award. Professor Hu has been recognized for his contributions in device physics, device modeling, and device reliability through BSIM and BERT models. More than a decade ago Hu and fellow researchers invented the revolutionary three-dimensional FinFET.
Mentor Graphics has announced hardware and software solutions to accelerate the verification of Serial Attached SCSI (SAS) second-generation (Gen2) products, having speeds up to 6Gbps. Using the Mentor® verification solutions, designers can test their SAS Gen2 devices integrated on their System-on-Chip (SoC) designs, and develop and test their software drivers and applications prior to silicon being available. The solutions consists of iSolveTM SAS, which has a ‘plug-and-play’ hardware interface to the Veloce® family of hardware emulators and a SAS transaction-based verification IP (VIP) solution.
Altera has demonstrated a programmable device with 32-Gbps transceiver capabilities. The demonstration uses a 20 nm device based on TSMC’s 20SoC process technology. This achievement validates the performance capabilities of 20 nm silicon. Today, Altera is shipping production 28 nm FPGAs with monolithically integrated low-power transceivers operating at 28 Gbps.
Mentor Graphics says it has an IP to system, UPF-based low-power verification flow. The IEEE-1801 UPF (Unified Power Format) has emerged as the low- power standard that enables designers to specify a design’s power intent separately from the design itself ensuring reuse, portability and greater flexibility in power management techniques. Mentor now has platform-level support of UPF in both the Questa® functional verification platform and the Veloce® family of hardware emulators that lets users create a single specification for power intent that is reusable and consistent, and facilitates low-power verification across simulation, formal and emulation.
ARM announced the availability of POP IP products for its ARMv8 architecture-based Cortex-A57 and Cortex-A53 processors for TSMC 28HPM process technology, as well as the roadmap for POP IP to TSMC’s 16nm FinFET process technology. An essential element of ARM’s implementation strategy, POP technology enables ARM partners to quickly close timing of dual- and quad-core implementations across a broad envelope of power, performance and area optimization points.
Imperas has released its latest software model, the ARM Cortex-A7 MPCore, to complement its existing range of ARM Cortex models. The model uses Imperas code morphing technology to allow software engineers to execute development code at hundreds of millions of instructions per second. Incorporated within the model is Imperas’ range of advanced development tools for efficient software analysis and debug.
Cypress Semiconductor has introduced PSoC® Creator™ 2.2, the integrated design environment (IDE) for Cypress’s PSoC 3 and PSoC 5LP architectures, along with a new Component Pack. The new release features seven new and five enhanced components including MDIO Interface, SAR Sequencer and a digital component pack with multiple Flip/Flops, a Pulse Converter and a Frequency Divider. It also offers a new PWM-based sensor interface component that connects to Analog Devices’ TMP05 temperature sensors. Version 2.2 adds easy import and export tools.
– keeping you covered
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