This past week, the OpenPDK Coalition at Si2 has released an important specification on electro-static discharge (ESD) design best practices to improve reliability for integrated circuits, particularly at advanced process nodes. This design methodology "best practices" document is the result of collaborative work by leading companies such as IBM, Intel, GLOBALFOUNDRIES, NXP, Samsung, and STMicroelectronics. It includes guidelines spanning schematic and layout level checks, power bus extraction, floorplanning checks, and tool infrastructure, and applies to designs at 130nm and below. It is freely available for download from: www.si2.org.
Many years ago, I was TI's reliability strategy manager, and was a member of the "CMOS Design Council" to define rules for new processes. It's a daunting job, because (as usual) the optimal rules for ease of manufacturing and best yield sometimes conflicted with economic and time-to-market needs for very popular existing product design families. I was always a noisy advocate for shifting more of the traditionally manual steps to much more streamlined automated techniques. I especially felt it was a disservice to only inform designers of errors at the very end of the process, leaving them with a heap of errors to correct (manually). My goal has been, and remains, to shift more from just awareness of a problem to avoidance, exploiting the abundance of automation tools in a flow and potential for helping designers discover and correct problems as early as practical. I am very glad that the OpenPDK Coalition has released these design guidelines to improve reliability and quality, starting from design capture.
Speaking of such things, I would like to call attention to a related "collaborative" event taking place next week: the International Reliability Physics Symposium (IRPS), being held April 16-18 in Monterey Beach, CA.
The IRPS program offers a rich, impressive technical program that covers a wide range of topics, from ESD protection, latchup, and electromigration to SPICE reliability modeling and circuit simulation, to statistical variability analysis and FLASH memory lifetimes, to hot carriers and soft errors, and much more.
Dr. Chenming Hu of UC Berkeley and TSMC fame will deliver a keynote on FinFET reliability, while Mathew Wallace of JPL-NASA will share reliability challenges and experiences in the interplanetary Mars Curiosity Rover mission.
Registration details can be found at: www.irps.org/conference-information.
Steve Schulz is president and CEO of Si2
More Collaborative Advantage blogs are available for your reading pleasure.
If you found this article to be of interest, visit EDA Designline
where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here
to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).