I think the practical end to in-house layout may be in sight. I say this for several reasons; complexity, learning curve, peak-load labor requirements and alternative use of manpower.
Letís take a look at each issue and see what one might conclude. I think I have it right, but who knows, maybe Iím the only one that sees the murky end to internal layout teams at most organizations.
Complexity is a hackneyed word. Itís more often an excuse than a condition. But at 28-nm process technology, and of course beyond, itís simply not your fatherís physical design.
It used to be we would declare that the chip was "done" when the netlist was verified. We all knew that layout was just an afterthought executed by some guy in the back room, the "tech," who in any other industry might wear a flannel shirt and carry a lunch pail.
Not today. A crack layout team is composed of approximately 12 to 24 very capable engineers, most with advanced degrees. Half of them will have specialized skills such signal integrity, high-speed I/O integration, DFT, package design (yes, this is now done up front and in complete coordination with the layout folks), A/MS expertise, SPICE modeling (always a help) and, of course, the power expert. To put it another way, the complexity of a 28-nm IC is stressing the very best of organizations. Just ask them.
When I refer to learning curve, Iím referring to the lack of one.
As we all know, there are fewer and fewer design starts today. The company that made the six-chip chipset now has them all crammed onto one die. After all, thatís why we chase the smaller geometries.
The implication of that is many reasonably large companies are making one, possibly two, chips per node per year or two. If thatís all you make, how do you ever get good at it? How do you perfect the recipe?
The fact is you don't! Besides, if you are to make one very expensive 28nm part, it better be close to perfect and certainly not require any significant re-engineering. Good often isnít good enough.
In fact, you are victims of lost scale, diminishing returns and a desire by your employees to avoid being assigned to an inefficient and likely ineffective task. How may engineers inside a company want to work on the in-house EDA staff? You get the picture.
Now letís take a look at peak-load engineering requirements.
By informal observation I can tell you that at 65-nm a robust design required between 3,000 and 4,000 hours of layout labor. At 40-nm the layout task consumed about 8,000 to 12,000 labor hours. At 28-nm, a typical IC can easily consume 20,000 to 30,000 hours of labor and we at eSilicon have two design currently scoped at 45,000 labor hours. The latter example is around 26 engineers working full time for one year.
Now, if there is a steady stream of these parts, those folks can move gracefully from one project to the next and labor utilization is under control. However, if your company does not have another layout ready to goÖguess what? You now have 20+ engineers with "nothing" to do. I put "nothing" in quotes because, as we all know, they will find something to do. It just may not be what the company needs, which brings me to the last topic: the alternative use of manpower.
This is not genius.
The simple question is whether you want your engineers to work on a task that can be addressed in the market place, hat they may not execute optimally due to lack of experience, which will result in sporadic utilization at best OR would you rather deploy those same engineering hours in the development of differentiating IP, architectures and software?
Hmmm, letís see. Do we even need to discuss this further? Well I won't.
Once upon a time all chip companies made EDA tools, owned fabs, and made all their own IP. However, we gave that all up in favor of specialized companies that aggregated the R&D, the skilled engineers and the financial economies of scale. Layout is the next casualty of this 25-year-old trend.
Simply stated, it makes no sense to perform layout in-house any more than it makes sense to develop an internal place-and-route tool. The best companies in the world know this already. The followers will soon be on board. The laggards will assume their rightful place in the semiconductor ecosystem as they have for forty years: producing suboptimal-performing product that is late to market with unacceptable quality. Jack Harding is President and CEO of eSilicon Corp. (Sunnyvale, Calif.), a design and manufacturing services company.
Having spent many years in ASIC support for customers doing high speed digital design I can say for sure that there was and needs to be a tight coupling between the design team and the layout group. All too often, the design team (working in Verilog/VHDL) was too disconnected from the physical ramifications of what they were coding that it took some "high energy" meetings between the designers and layout groups to work on finding a solution. Often times there were many trade offs being made live over the layout/placement with the needed visual feedback, I can't imagine having an optimal solution with a large physical/cultural/language separation.
Indeed. Many of us working on the front end side of IC design never liked the idea of "throw it over the wall" to the backend team, even in the days when that was more feasible. Too much loss of communication and feedback between the two teams usually leads to a suboptimal result.
Even the author's own observations -- the need for expertise in signal integrity, high-speed I/O integration, DFT, package design, etc on the backend team makes the argument even more powerful that it is not a good idea to just throw the database over the wall to the backend team, cross your fingers and hope for the best.
Nothing beats co-location, and that can only be accomplished with an in-house backend team.
I wonder how many of those out-house layout teams are out there. With foundries clampping on information (design rules, models, etc.), what would be a viable path for such companies to survive? The only way seems to be for foundries to take over design.
Automated analog layout has always lagged digital layout until now. This task can be completed in a manner of minutes versus weeks due to an optimization process incorporated into a software by Analog Rails. Comment as you wish on this being a commercial or look at the solution that will considerably shorten design times.
I too disagree with this article. In my 16 years of experience, the continual increase in process and EDA tool complexity (see cadence 5.1 to 6.1 transition) has made the need for a local layout team even more important.
Moronda is dead on, another sales pitch from Jack Harding about eSilicon, we gave these guys a tried. They don't have many of the capabilities that they claimed, and not that good at what they do have. This guy is a baffoon, and there a lot better design services company out there.
I'm sorry but this is obviously a total sales pitch from esilicon. Here's how I read this story. Layout is really tough and we here at esilicon know what we are doing. So quit doing layout at your company, fire all your layout engineers, and farm it out to us. Come spend millions of dollars at esilicon. Then, we will also up sell you on the rest of our services like IP and manufacturing.
I think outsourcing can be a big pain in the butt. There is nothing that says it can't go bad too. What if I get your worst layout team on my project? I don't want to be on the phone with a bunch of people that barely speak english.
Harding, what have you done at esilicon? Why are you still private? Why haven't you gone public or been acquired? You've been around for years and years. What's going on there? If I was lead investor in esilicon, I would fire you for not closing on a successful exit.
I think these board of directors are just clueless sometimes. Crosspoint, Crescendo, Fremont, Investor Growth, don't you want a return on your investment? Why is this guy still in charge? Hold someone accountable for not executing to an acquisition or IPO.
My guess is that nobody cares about acquiring a design services company. There is huge competition in that space.
But say for high speed circuits, RF or analog designs, it is quite necessary for the layout and circuit guys sit close to each other. Our circuit team benefitted in terms of turn around time because the layout engineer was sitting in a neighbouring cubicle. I somehow feel that the quality will suffer if the layout moves out of the team.
I think you are right for fabless companies. For the major semiconductor companies that develop their own processes, they need to build their own standard cell libraries. This is a very powerful tool for competitiveness. I have seen similar chips from two companies with big differences in size due to the basic cell even though the process was similar. I don't see IDMs moving away from internal layout.
Statistically speaking, I think you may be correct. But, there is a lot to be said to having a "tight" coupling between architecture and layout. Having done back end stuff for 25+ years I can't tell you how many times the architects thought they had Carte Blanche over what they could do and include on the die. It was only after many very energetic face to face "dungeon" like sessions where we met a happy middle ground.
When the backend is isolated like this, I'm sure assembling a bunch of hard IP around some on chip interconnect/fabric at frequencies/power/area that may not be pushing the envelope the 1st pass is fine. But other then that, you're going to really benefit by having that close communication between architecture/logic/layout/circuits.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for todayís commercial processor giants such as Intel, ARM and Imagination Technologies.