I think the practical end to in-house layout may be in sight. I say this for several reasons; complexity, learning curve, peak-load labor requirements and alternative use of manpower.
Letís take a look at each issue and see what one might conclude. I think I have it right, but who knows, maybe Iím the only one that sees the murky end to internal layout teams at most organizations.
Complexity is a hackneyed word. Itís more often an excuse than a condition. But at 28-nm process technology, and of course beyond, itís simply not your fatherís physical design.
It used to be we would declare that the chip was "done" when the netlist was verified. We all knew that layout was just an afterthought executed by some guy in the back room, the "tech," who in any other industry might wear a flannel shirt and carry a lunch pail.
Not today. A crack layout team is composed of approximately 12 to 24 very capable engineers, most with advanced degrees. Half of them will have specialized skills such signal integrity, high-speed I/O integration, DFT, package design (yes, this is now done up front and in complete coordination with the layout folks), A/MS expertise, SPICE modeling (always a help) and, of course, the power expert. To put it another way, the complexity of a 28-nm IC is stressing the very best of organizations. Just ask them.
When I refer to learning curve, Iím referring to the lack of one.
As we all know, there are fewer and fewer design starts today. The company that made the six-chip chipset now has them all crammed onto one die. After all, thatís why we chase the smaller geometries.
The implication of that is many reasonably large companies are making one, possibly two, chips per node per year or two. If thatís all you make, how do you ever get good at it? How do you perfect the recipe?
The fact is you don't! Besides, if you are to make one very expensive 28nm part, it better be close to perfect and certainly not require any significant re-engineering. Good often isnít good enough.
In fact, you are victims of lost scale, diminishing returns and a desire by your employees to avoid being assigned to an inefficient and likely ineffective task. How may engineers inside a company want to work on the in-house EDA staff? You get the picture.
Now letís take a look at peak-load engineering requirements.
By informal observation I can tell you that at 65-nm a robust design required between 3,000 and 4,000 hours of layout labor. At 40-nm the layout task consumed about 8,000 to 12,000 labor hours. At 28-nm, a typical IC can easily consume 20,000 to 30,000 hours of labor and we at eSilicon have two design currently scoped at 45,000 labor hours. The latter example is around 26 engineers working full time for one year.
Now, if there is a steady stream of these parts, those folks can move gracefully from one project to the next and labor utilization is under control. However, if your company does not have another layout ready to goÖguess what? You now have 20+ engineers with "nothing" to do. I put "nothing" in quotes because, as we all know, they will find something to do. It just may not be what the company needs, which brings me to the last topic: the alternative use of manpower.
This is not genius.
The simple question is whether you want your engineers to work on a task that can be addressed in the market place, hat they may not execute optimally due to lack of experience, which will result in sporadic utilization at best OR would you rather deploy those same engineering hours in the development of differentiating IP, architectures and software?
Hmmm, letís see. Do we even need to discuss this further? Well I won't.
Once upon a time all chip companies made EDA tools, owned fabs, and made all their own IP. However, we gave that all up in favor of specialized companies that aggregated the R&D, the skilled engineers and the financial economies of scale. Layout is the next casualty of this 25-year-old trend.
Simply stated, it makes no sense to perform layout in-house any more than it makes sense to develop an internal place-and-route tool. The best companies in the world know this already. The followers will soon be on board. The laggards will assume their rightful place in the semiconductor ecosystem as they have for forty years: producing suboptimal-performing product that is late to market with unacceptable quality.
Jack Harding is President and CEO of eSilicon Corp. (Sunnyvale, Calif.), a design and manufacturing services company.