This is a roundup of news or activities in the past few days that may be of interest to people.
Space Codesign Systems and Hardent are proud to announce a new training course on electronic system level (ESL) methodology and Hardware/Software Co-design for the Xilinx Zynq “All Programmable SoC” platform. This course shows how the Xilinx Zynq “All Programmable SoC” platform can be abstracted and modeled in a fully functional software representation of a hardware/software SoC design based on a mix of processors (Cortex-A9 dual MPCore and MicroBlaze), software, communication links (AXI interconnects), memories, and other IP cores.
Synopsys' new 2013.03 version of Synphony Model Compiler introduces new features for both FPGA and ASIC design flows. The new features include new FFT2 block that improves throughput with parallel mode up to 32 inputs, in addition to streaming mode. Improved DSP mapping on advanced Xilinx and Altera devices, new host interface that provides integration of memory-mapped interfaces to multirate Synphony Model Compiler designs, updates in FIR2 and DDS2 blocks and SystemC wrappers that are now automatically generated with C/C++ model generation.
Offering the opportunity to enter the Design Automation Conference (DAC) and be part of the celebration, Atrenta, Jasper Design Automation, and Forte Design Systems are sponsoring three-day exhibit passes through the fifth annual "I LOVE DAC" campaign. DAC is celebrating its 50th year as the premier conference devoted to electronic design, design automation, embedded systems and software. This golden year for DAC will be filled with exciting exhibits, riveting keynotes, Designed in Texas sessions, networking events and much more. The conference and exhibition will be held at the Austin Convention Center in Austin, Texas from June 2-6, 2013.
Flexras Technologies has announced the release 3.2 of its WasgaTMCompiler Design Suite for FPGA-based prototyping. This new release supports the Xilinx® Virtex®-7 FPGA and includes new features that accelerate SoC rapid prototyping. Enhancements include Virtex-7 FPGA Advanced Pin Multiplexing using Serdes and LVDS, Automatic generation of XDC pin-planning and timing constraints for Vivado Design Suite, Logic replication and pruning to optimize connectivity between FPGAs and modeling of inter-FPGA configurable cables.
Symtavision has announced the addition of Ethernet timing analysis to its SymTA/S tool for the design and verification of embedded real-time systems. The new Ethernet timing analysis targets the automotive market and integrates seamlessly with the existing in-vehicle network timing analyses for CAN and FlexRay as well as with scheduling analysis for AUTOSAR-based ECUs.
Altera and TSMC have announced a technology collaboration using TSMC’s 55 nm Embedded Flash (EmbFlash) process technology. Compared to prior generation embedded flash, TSMC’s 55 nm EmbFlash delivers faster computing, increases gate density 10 times and shrinks flash and SRAM cell sizes by 70 percent and 80 percent respectively.
Accellera has completed its IP Tagging 1.0 standard. The standard provides a mechanism to track critical soft IP data throughout the entire chip design and development process such that it can be readily identified, tagged, and used again for future designs. Using the Soft IP Tagging 1.0 standard, engineers now have the ability to easily determine if a block of IP is contained within a chip, if it is the correct version, and if it is a candidate for reuse. In addition, semiconductor foundries, providers of IP, and manufacturers of design tools now have a standard way to track IP usage and royalty information with their customers. Find out more and download the standard under open source license at www.accellera.org.
Gold Standard Simulations revealed today that the interplay between the effects of statistical reliability and variability could adversely affect 20nm CMOS SRAM yield. The study also defined a new reliability simulation framework to predict variability and reliability impact that enhances yield. According to the study, the interplay amongst individual trapped charges with random discrete dopants, line edge roughness and metal gate granularity in 20nm CMOS transistors leads to wide dispersions in transistors characteristics and to gigantic random telegraph noise amplitudes that adversely affect SRAM yield and reliability. Even a single trapped electron can disturb the information stored in an SRAM memory cell. A newly-developed Kinetic Monte Carlo reliability simulation engine enables seamless statistical simulation of Bias Temperature Instability, random telegraph noise and Trap-Assisted Tunneling.
Semico Research has a new study out that examines advances in the 3rd Party Semiconductor Intellectual Property market as well as in the EDA market that have allowed silicon designers to increase the complexity in their silicon solutions to the point where the industry can actually think about these solutions in the plural sense, as System(s)-on-a-Chip (SoC). The trend towards higher complexity applications has confirmed the SoC design methodology as the methodology of choice for silicon designers and architects to accomplish their silicon solutions. The acceptance of the SoC design methodology has led to a 12.6% increase in 2012 unit shipments and a forecasted 11.5% increase in 2013 shipments with forecasted revenues for 2013 increasing 12.2% to reach $92.9B. Semico believes advances in the SIP and EDA markets will continue to allow more complex and converged architectures in the SoC market. Ultimately, this means that SoC solutions will better mirror end-market requirements for feature sets and functionality, and that there is room for innovative products to continue to enter the electronics market.
ARM has announced a new licensing model to enable broader access to big.LITTLE™ processing technology for ARM partners. Under the terms of a single use design license, ARM partners can license the individual components required to enable the development of a big.LITTLE system, including the ARM Cortex®-A15 and Cortex-A7 processors; the CoreLink™ Cache Coherent Interconnect (CCI-400); the Generic Interrupt Controller (GIC-400) and the AMBA® Domain Bridge (ADB-400), all as a single package.Brian Bailey
– keeping you covered
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