ARM, Aspen Labs, CEVA, Corelis, Digi-Key, EDAC, IC Manage and Mouser made the lineup today. See here for their news...
This is a roundup of news or activities in the past few days that may be of interest to people.
Aspen Labs and global electronic components distributor Digi-Key Corporation are giving engineers access to a new set of free, online CAD tools to support Printed Circuit Board (PCB) design and development. Aspen Labs engaged with Digi-Key as an exclusive integration partner because of the company’s breadth of in-stock electronic components. PCBWeb aims to help engineers move projects from the earliest stages all the way through to a finished hardware design, ready to send off for production. The tool features multi-sheet schematic capture, multi-layer PCB layout with DRC, a component editor and is integrated with Digi-Key suppliers.
CEVA has introduced a new low-energy software framework for Android based systems, which reduces the power consumption required for complex multimedia processing using a heterogeneous CPU and DSP system architecture. Known as Android Multimedia Framework, the framework addresses the most intensive, real-time signal processing applications, including audio, voice, imaging and vision, and seamlessly offloads the related tasks from the CPU to the CEVA DSPs at the Android Operation System (OS) level. Previously, the DSP was detached from the Android OS, requiring system programmers to implement multimedia tasks and partitioning at the CPU level, resulting in inefficient use of the CPU to perform complex, power hungry DSP tasks.
Joe Costello is set to shares his secrets for communicating a compelling company story in the next installment of the EDAC - Jim Hogan Emerging Companies Series. These conversations explore concepts and best practices for emerging companies. A company’s success goes beyond top-rate, innovative technology. It also needs that “X factor” where its vision and story resonate deeply with its target audience. The goal of this event is to guide entrepreneurs on the key elements of creating and telling a compelling technology or company story. As with past sessions, the format will be a conversation between the speakers, after which Jim Hogan will open the discussion for audience questions. May 1st in San Jose. More information here.
Corelis has announced the availability of version 7.8 of its ScanExpress boundary-scan tool suite. This new version includes improved cluster testing support, intelligent BSDL file handling, and a new model-based test coverage. The new version also expands JTAG Embedded Test (JET) support to Texas Instruments AM335x Sitara™ processors.
Mouser Electronics, Digi-Key and I am sure other distributors are now talking about the new BeagleBone Black from CircuitCo, a lower-cost, high-expansion focused BeagleBone featuring a Sitara AM335x Cortex A8 ARM processor from Texas Instruments. This is the newest member of the BeagleBoard family features an upgraded 1-GHz Sitara™ AM335x ARM® Cortex™-A8 processor from Texas Instruments Incorporated (TI), 512 MB DDR3 system memory, reduced power consumption and the addition of HDMI connectivity.
ARM has extended the scope of the ARM Development Studio 5 (DS-5™) Community Edition (CE) to provide a fully featured, industry standard, and free-to-use software development environment for ARM Embedded Linux applications. DS-5 CE provides an integrated solution including an Eclipse IDE, GNU cross-compiler, DS-5 Debugger, Streamline™ performance analyzer, online help and software examples.
IC Manage announces its fifth annual Global Design Management Report. This year’s report is on IP Reuse – Design and Verification and covers the results of a 372 respondent survey of SOC and IC design professionals; it spans design reuse, verification reuse, and dependency management. The findings survey include: Non-Memory SoC & IC design composition, IP Reuse and Verification, Top IP reuse dependency management challenges, Percentage of tape outs with known bugs, Measured ROI from IP reuse dependency management system and Organizational incentives to increase internal IP reuse. Early result from this report were released on the EDA Designline at the beginning of the month.
– keeping you covered
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