Addressing new extraction accuracy, complexity, and computational requirements at 20 nm and below...
As major foundries announce the release of their 1.0 versions of 20 nm processes, we now see IC designers moving to production design and implementation of integrated circuits at this node. For many companies, test chips are complete, IP is developed, and process flows are defined. The challenge now shifts from characterization, modeling, and other activities needed to define the feasibility of a new process node to actually taping out production chips on the new technology. For any new process, there are the customary concerns such as design complexity, electrical behavior modeling, and the definition of new physical implementation and verification techniques that will deliver the most robust designs. Additionally, there are node-specific challenges driven by new manufacturing techniques that create new requirements for design rule checking (DRC), design for manufacturing (DFM), physical implementation, and parasitic extraction. At 20 nm, the node-specific challenge is double-patterning (DP), and physical implementation teams are wrestling with how to achieve timing and electrical sign-off under this new paradigm.
The need for DP at 20 nm has been well documented. To achieve better fidelity of 20 nm designs, we need to decompose individual layers into 2 separate masks and perform the lithography for a given layer in 2 distinct steps. This technology will evolve to triple patterning and multi-patterning at newer nodes, and is the catalyst for new techniques in design and verification tools. Now, as we move towards production tape-outs at 20 nm, questions arise regarding the electrical implications of DP. With layers being decomposed into different masks, will there be new sources of variation? If so, how do we account for that variation, and what impact will that have for static timing analysis (STA), signal integration (SI), and power analysis (PA)? And, if there are new requirements, how can they be addressed without increasing the time spent in the tape-out analysis flow? Parasitic Extraction (PEX) represents the input to electrical analysis flows, so determining the impact of DP on electrical sign-off can be better achieved by understanding how PEX tools have evolved to handle this challenge.
There are two main innovations for PEX tools that address DP:
- Modeling to account for variation due to mask misalignment
- More efficient processing to maintain reasonable cycle time for electrical sign-off
Modeling for mask misalignment
With DP, there will be additional sources of variation. The light and dark blue lines in Figure 1 depict metal wires on the same layer, but the different colors indicate that they reside on different masks. During lithography, these masks may not be perfectly aligned, and any misalignment in the x, y, or z direction will have an impact on parasitic capacitance calculation. The red regions indicate where coupling capacitances increase, and the orange regions are an indication of decreased coupling capacitances, due to mask shifts. Compared to perfectly aligned masks, a 2 nm offset could have a 5% impact on coupling capacitance values, while a 6 nm shift could result in differences as high as 20%. The challenge is to quantify the mask shifts appropriately, and incorporate that shift into the capacitance calculation.
Figure 1: Mask shifts will affect capacitance modeling.
IC manufacturers have worked very hard to quantify the amount DP masks will shift, and are working just as hard to keep that shift to a 1-2 nm delta. Using foundry data, PEX tools have developed corner methodologies to account for the differences between typical alignment, as well as shifts in the x, y, and z directions. As with traditional interconnect corners, DP corners are used to place bounds on the amount of capacitance variation that will be seen, which means if a design passes sign-off requirements across the range of DP corners, then the manufactured silicon will be robust against process differences and still perform to specification.
Additionally, to prevent overly conservative results from parasitic extraction, PEX tools have evolved to incorporate “colored” layout and to make color assignments. Coloring is the process used by physical implementation and physical variation tools to assign different wires to different masks. This is a necessary function for implementation and verification tools because there are different DRC and DFM requirements based on the mask assignment for wires. For PEX, wires on the same mask will not have variation respective to each other, based on DP. It is the wires on different masks that need the additional computation. By incorporating colored layout, PEX tools can apply the analysis only where it is necessary, and develop variation or corner models for the wires on different masks to accurately represent the variation that is possible across all corners of the design.
More efficient processing
One obvious implication of DP for PEX is more corners. In fact, there are now corners within corners. For each typical process corner, there can be as many as 3 DP corners. At 28 nm, most IC manufacturers were recommending 5 process corners (typical, C Best, C worst, RC best, and RC worst). At 20 nm, there can be as many as 15 corners (including DP), and most foundries are offering 11. Since designs are also growing in complexity at each successive node, a big challenge for PEX at 20 nm is processing the design and the necessary corners without incurring additional cycle time for the sign-off flow.
Traditionally, each corner means a full run of the PEX tool. Therefore, 5 corners requires 5X the runtime of a single corner, and 11 corners requires 11 times the runtime. Using traditional methods, the 20 nm designer would have to incur either 2X the runtime or 2X the hardware of a 28 nm design. A better solution is more efficient processing. Most of the computation time in PEX is spent processing the physical design. The design is the same as 28 nm, and the only difference between the various corners is the spacing or dimension of the wires. The variation from corner to corner is captured in either tables or equations, depending on the foundry or the PEX tool. Modern PEX tools can process all corners simultaneously to incur only minimal additional run time. Figure 2 shows a PEX tool that incurs 4% additional runtime per corner with no impact on accuracy, meaning 11 corners can be processed in less than 1.5X the runtime of a single corner. With this type of tool, complete corner processing can be achieved more quickly at 20 nm than with the use of a traditional tool at 28 nm.
Figure 2: Traditional corner processing vs. newer, more efficient methods.
Overall, DP has a profound impact on PEX and subsequent electrical analysis flows. However, with new modeling techniques and more efficient processing, the industry will improve sign-off methodologies without loss of accuracy or incurring additional turnaround time. As one of my colleagues likes to say, “Each new node is a dry run for the next run.” If that’s true, then these developments are fortuitous, since the next nodes will bring the challenges of triple patterning and FinFets…
About the author
Carey Robertson is a Director of Product Marketing at Mentor Graphics Corp., overseeing the marketing activities for Calibre PERC, LVS and extraction products. He has been with Mentor Graphics for 15 years in various product and technical marketing roles. Prior to Mentor Graphics, Carey was a design engineer at Digital Equipment Corp., working on microprocessor design. Carey holds a BS from Stanford University and an MS from UC Berkeley. He may be contacted at firstname.lastname@example.org.
Additional blogs from Carey Robertson and Mentor Graphics can be found here.
Recent Carey Robertson blogs include:
Interconnect Modeling at 20nm – More of the Same or Completely Different? Calibre PERC: Preventing Electrical Overstress Failures
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