In electronics, configurable and adaptive are terms often associated with field programmable gate arrays (FPGAs) and not blocks of intellectual property (IP). And just like configurable FPGAs were 20 years ago, adaptive IP is the wave of the future.
More and more often, system-on-chip (SoC) designs make use of third-party IP. So much so, that surveys peg the percentage of IP content in a typical SoC at 70% or more, with many of these SoCs implemented in more advanced process nodes. At 28 nanometer (nm), process variation effects and dynamic variations due to fluctuating operating conditions may obstruct system performance or cause system instability. This is where implementing adaptive IP can help. It automatically compensates for the effects of static and dynamic variations and allows a system to achieve its best performance, while maintaining a high degree of reliability.
Managing static and dynamic variations is one of the many considerations for designers when they’re implementing an SoC design in an advanced process node. These subtle variations are becoming the most important considerations for a number of reasons.
Static variations are a consequence of the chip manufacturing process where no two devices behave exactly the same. Careful design planning and execution to accommodate small differences across the expected behavior from a population of devices is needed to ensure that the finished product performs as expected.
The chip is only the beginning. The package, printed circuit board (PCB) or other system substrate and external components that interface with the chip have their own static variations that must be factored into the design when considering overall system performance and reliability.
Dynamic variations in operation are due to fluctuations in the system environment that include temperature or voltage, difficult environmental variables to predict, but variables a system must be designed to withstand in the field nonetheless. Consequently, performance may be sacrificed if the design specification is set to manage a wide range of anticipated operating conditions. Conversely, the system could suffer from reliability problems if operating conditions are met outside the expected norm if the system is designed for performance.
A designer’s goal is to ensure that the device or system meets performance and reliability goals. He or she spends time testing and evaluating a system using examples from different operating conditions with a goal to “tune” the device or system so it will operate across the expected range of static and dynamic variations encountered by the consumer.
Adaptive IP can make all the difference because it can measure the relevant parameters critical to performance and reliability, then automatically make adjustments to ensure the parameters are optimized. These precise measurements and corrections would be made during system initialization and again at regular times during system operation.
Adaptive routines run quickly and have little impact on system operation and throughput, and have enough latitude to correct for a wide range of variation. Because adaptive IP is in the chip, each system is optimized for static variations in each component and dynamic variations caused by the system environment. That means, the chip continually optimizes its operation to deliver the best performance with robustness and reliability to the consumer.
Consider the DDR memory subsystem found in most SoCs as adaptive IP. Designing a high-performance, reliable DDR interface is no small feat because its interface is often the highest frequency interface in the system and, if it fails or is unstable, the system becomes unusable.
Of course, designers look to a variety of training routines specified within the JEDEC DDR memory specifications. They will not find a solution to the clock domain crossing problem during a read operation that ensures the data strobe (DQS) generated by the DDR SDRAM and associated data can be synchronized with the SoC system clock. The relationship between the phase and latency of these clock domains is subject to static and dynamic variations and difficult to predict or model.
Typically, designers deploy a DDR subsystem to bench test and measure multiple systems with multiple components across a variety of operating corners. Decisions are made about how to set up the interface timing once they have enough data, making it likely that all systems will perform across tested scenarios. However, it can take days, weeks or months with np guarantee that each system will perform perfectly in every operating scenario.
The solution is DDR adaptive IP. During system initialization, the adaptive IP measures phase and latency differences between the data strobe signal (DQS) and the SoC clock and programs the interface to align the two domains for that specific system. During system operation, the adaptive IP periodically rechecks the phase and latency and, if needed, re-calibrates the timing.
Using this approach, system bring-up is automated because the adaptive IP finds the best operating point for each device and system. The use of adaptive IP allows the best system performance to be achieved and ensures that the system maintains stable operation under varying operating conditions.
Adaptive IP is being adopted today. This may mean that in 20 years or so, the electronics industry will view adaptive IP as a mainstream concept much as we now view FPGAs. Will the wave of the future being adaptive silicon? Anything’s possible!
About the author
Josh Lee is president and CEO of Uniquify in San Jose, Calif. Lee holds a Bachelor of Science degree in Electrical Engineering and Computer Sciences from the University of California, Berkeley.
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