SoC designers need better IP quality! They need a system to check the overall quality of the delivered IP, similar to a Consumer Reports analysis...
As an SoC designer, you’re probably frustrated by how IP (3rd party and internal) can hinder your design getting to tapeout. After all, IP is supposed to be the cure-all for increasingly-complex SoC designs, right? However, it’s turned into a sometimes endless, difficult series of IP fixes. Why?
The answer is simple – it’s all about quality. Let’s think about this: the quality of today’s IP varies widely. SoC designers never know whether they will be able to use an IP block in multiple designs or if they will have a problem designing an IP block into just one design. SoC designers need better IP quality! They need a system to check the overall quality of the delivered IP, similar to a Consumer Reports analysis. And this analysis should enforce a quality standard so that the consumer has confidence that an IP block won't require difficult and time-consuming tweaks and fixes to work in the target design.
To ensure IP quality, design projects need to create such a Consumer Reports methodology. How do we get there? Here are some suggestions.
First of all, consider what IP is supposed to do. Basically, an IP block has to: (1) meet its functional requirements and adhere to the protocol or spec, and (2) successfully integrate into the target chip or sub-system. High quality IP will get you to tapeout much faster. Lower quality IP will require you to go in and fix the IP so that it functions in your particular design correctly. These are the IP blocks with black circles next to them, using the standard Consumer Reports icons.
As a designer, you’ll need a few releases to stabilize support for a spec change in your IP. If you multiply this by several IPs you are using in your design and more than one possible problem per IP, you can see how this can get out of control pretty quickly. You can’t re-run a full evaluation on each change, but you also can’t afford to expose your design to incoming changes of unknown quality. So what you need is a scripted system you can run across the entire IP library, checking for what changed and flagging only when an IP changes in some suspicious manner. This is the unabridged Consumer Reports analysis.
In an ideal world, you should run each incoming release through the full suite of tools that will be used in the design assembly, verification and implementation flow. Such tools include static quality checks, simulation, synthesis, timing analysis and ATPG. IP development organizations/companies do this, or should.
The challenge for an IP user is that setting up this type of checking is extremely difficult. It takes up to a week to run and will probably be redundant. Not everyone can set up a complete Consumer Reports laboratory. You’ll need to make some tradeoff decisions:
- You must do some level of checking or you will be completely exposed.
- Nevertheless, no matter how hard you try, some problems will only be detected in design assembly/verification/implementation.
- Thus you need to balance how hard you try against the delay in getting to use a new release. (Think about how much delay you’re prepared to tolerate versus the potential hit of a problem you might have detected on inspection.)
- You will probably opt for the best quality assessment you can get quickly, especially if the method can be fine-tuned (with experience) to minimize significant escapes.
Your charge will be to figure out what is the best IP quality assessment you can get in a timely manner. One solution is to run production tools to check for quality. Another option is to run static quality assessments – lint, domain crossing analysis, power constraint validation, testability metrics and SDC quality checks – which can all be run with minimal setup and in short runtime per IP block.
What about functionality? Is it possible to quickly check that the function of an IP wasn’t disrupted in some subtle way? Formal verification may provide some help on small blocks or specific checks, but writing assertions requires a lot of human effort and expertise. Running the supplier’s testbench seems redundant, and constrained-random verification only goes so far. What you need is a more automatic way to capture the verification intent of the IP which can be achieved with innovative techniques like assertion synthesis. Fine-grained high quality assertions can capture the inherent functional specification of the IP and generate an SoC-level verification that is much more predictable. We’re back to the very desirable and clear “pass/fail” Consumer Reports analysis.
Ultimately, as a designer or design project manager, you need predictability of results so that you can hit your tapeout milestones. Putting in place a methodology based on objective quality criteria that can be measured and enforced will give you better control over the design project schedule because you’ll get fewer surprises from your IP.
IP quality is not something that either design managers or designers can retrofit into the design flow. What’s needed is a methodology to manage design quality at each stage of the design, from spec, to architecture, to RTL, and all the way down to silicon. The pursuit for IP quality must start from the beginning of a project, when the design methodology is being defined. Doing it this way gives you a chance to have clear, objective measurement at every step. And that, in turn, will result in better schedule predictability and lower costs.
About the author
Piyush Sancheti is the Vice President of Product Marketing at Atrenta Inc. He has over 18 years of experience in marketing, sales, business development and engineering. He has previously held senior positions at Cadence Design Systems, SentÃ© and Sequence Design. Mr. Sancheti brings a rich background in product strategy, new product launch, product management, major account management, and customer expansion strategies. He holds a Master of Science in Computer Engineering from Iowa State University and a Bachelor of Electronics & Telecommunication Engineering from the University of Indore, India.
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