Agilent, AMD, Cadence, CircuitSutra, ClioSoft, eMemory, Evatronix, Fishtail, Forte, MOSIS and Synopsys made the lineup today. See here for their news...
This is a roundup of news or activities in the past few days that may be of interest to people.
CircuitSutra has announced the release of their SystemC model library consisting of CircuitSutra Modeling Library (CSTML) and the Virtual Platform - Quick Start Package (VP-QSP), which can be used in the Virtual Platform project. CSTML is a library built on top of SystemC & TLM2.0. It is a collection of convenience classes and utilities that ease the model development activity. Virtual Platform - Quick Start Package (VP-QSP) is library of basic models and modeling infrastructure that can be used to quick start a virtual platform project.
MOSIS, a provider of low-cost prototyping and small volume production services for custom ICs, teams up with ePIXfab, the European Silicon Photonics support center providing low-cost prototyping services for photonic ICs. The partnership gives MOSIS' customers access to imec’s state-of-the-art fully integrated silicon photonics processes and Tyndall’s advanced silicon photonics packaging technology. The first ePIXfab-Europractice run for passive silicon photonics ICs is open for registration from June 2013 with design deadline September 9th 2013. MOSIS' customers can register for this run and obtain the design kit via MOSIS in June 2013.
AMD has announced a strategic focus on developing one-of-a-kind solutions through its Semi-Custom Business Unit based on the set of intellectual property (IP) across AMD processors, graphics and multimedia. The business unit will provide customer-centric design by integrating these building blocks with customer-specific IP to create tailor-made solutions using a flexible System-on-a-Chip (SoC) design methodology.
Synopsys has announced the 2013.03 release of its IC Compiler™ software. New features include optimizations to enable high-speed design, efficient implementation of final-stage engineering change orders (ECO) and fully color-ready, tapeout-proven support for the emerging FinFET-based silicon processes.
Cadence intends to acquire the IP business of Evatronix, adding to its expanding IP offering. Based in Poland, Evatronix delivers a silicon-proven IP portfolio, which includes certified USB 2.0/3.0, Display, MIPI, and storage controllers. The acquisition is expected to close in the second quarter of 2013. Terms of the transaction were not disclosed.
Cadence also has a new version of Incisive® Enterprise Simulator, with features that improve low-power verification productivity of complex SoCs by 30 percent. The 13.1 release addresses low-power verification challenges for advanced modeling, debug, power format support and to provide faster verification. The new debug features in Incisive SimVision Debugger provide simple visualization and interactive debug of both complex text-based power intent standards.
Forte Design Systems has launched the Forte Design Systems Channel (www.youtube.com/ForteDesignSystems) on YouTube as part of its enhanced education and training program. The channel, with a growing number of videos, addresses a range of topics related to SystemC, High-Level Synthesis (HLS) and Forte’s SystemC-based HLS offering Cynthesizer™. Popular videos include “An overview of HLS” and “An introduction to SystemC for Verilog coders.”
FishTail Design Automation has joined the Cadence Connections® program. FishTail has developed a flow that allows engineers to use Cadence® Encounter® Timing System to verify the quality of manual or automatically generated merged-mode constraints relative to multi-mode signoff constraints.
ClioSoft today introduced SOS viaADS, a new product resulting from a joint development effort between ClioSoft and Agilent Technologies. The solution integrates ClioSoft’s SOS Design Collaboration platform into Agilent’s Advanced Design System (ADS) to provide version control and enterprise wide design management. Users have easy right-click menu access to version control capabilities within the standard ADS user interface.
eMemory has announces an anti-fuse eNVM technology, NeoFuse. NeoFuse technology has been demonstrated in a number of first-tier foundries. The NeoFuse IP has been also approved on variety of advanced process nodes (65nm, 55nm, 40nm, 28nm) for different applications, such as low-power and high-voltage applications. NeoFuse utilizes an anti-fuse structure that stores data through the impedance change of the memory cell during the programming operation.
– keeping you covered
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