This is the first in a series of industry feedback I received from an IP survey sent out some weeks ago. Today the question is what will the IP landscape look like in the future...
When I was preparing for the IP focus period, I send out a set of question to many people in the industry. If you did not get those questions sent to you and would like to receive such calls for input in the future, just drop me an email and I will add you to my distribution list.
I will be providing the responses I received in a series of articles. Today the question is:
When the 3rd party IP market/business was first conceived, it was a bunch of small startups plus a few more established players. Significant consolidation has happened and a lot of IP is now supplied by the EDA companies. What do you think the IP landscape will look like in the future? Who owns it?
Michael Munsey, Director of Product Management, Semiconductor Solutions at Dassault Systčmes.
I believe that we are at an inflection point in the industry and we are about to see significant changes in the IP landscape. With new chip design costs approaching $100M and the capital investment needed to maintain a fab for future process nodes approaching $3B, more and more fabless and IDM’s will begin to change their business model and become IP suppliers. A few of the traditional chip design companies will move towards a design methodology that will involve more and more IP integration.
John Koeter, Vice President of Marketing, Solutions Group, Synopsys
We believe that the third-party design IP market will continue to grow, driven by schedule compression, core versus context decisions and design complexity. Physical implementation of IP blocks is getting even more complex as we head to FinFET. In order to develop high-quality physical IP on advanced process nodes, Synopsys believes that an IP provider needs to have the scale to be able to afford the required investment in high-quality design, verification, silicon characterization, and compliance methods. Similarly, interface standards are evolving rapidly. Widely used protocols such as USB, PCI Express, DDR, HDMI and others constantly undergo major revisions. The verification requirements are skyrocketing. Again, it takes scale to invest in the quality required to meet our customers’ high expectations. We also see a growing demand for higher complexity IP, what we call IP subsystems. Successful IP providers need to create more complex IP, including the software layers and high-level abstraction views. For example, Synopsys’ DesignWare® SoundWave Audio Subsystem incorporates programmable hardware, a GStreamer interface and virtual and physical prototyping models.
Susan Peterson, Product Marketing Group Director and Tom Hackett, Senior Product Marketing Manager, Cadence
IP is one of the elements required to quickly and efficiently develop the SoC of the future. As such, SoC developers are increasingly seeking IPs that:
- Are integration-optimized
- Solve analog and mixed-signal issues
- Are customized to their implementation
- Provide firmware stacks that are easy to hook up to their software
So the IP landscape is no longer going to be about simply having IP. People are looking to IP providers to deliver more. In addition to the points above, designers are also seeking verification IP to help them verify their SoCs, as well as IPs that solve challenges associated with advanced process technologies, like FinFETs.
Bernard Murphy, CTO of Atrenta Inc.
Always likely to be a mix of EDA and IP-only companies. The EDA companies will do a good job of managing the supermarket part of the business, but they are unlikely to drive new or star-IP: ARM, Imagination Tech, security, etc.
Mike Gianfagna, VP of Corporate Marketing at Atrenta Inc.
I would like to think that the suppliers who deliver high quality, predictable and easy-to-integrate IP will win, and there will be more of them over time due to the rising need for third party IP and the specialization that will bring. All this assumes there is a way to measure and report the quality of IP deliverables. This is an important area that needs focus and attention from everyone in the IP ecosystem.
Eran Briman, VP of Marketing CEVA
When it comes to EDA companies offering IPs, there could be 3 types: generic / commodity IPs such as memory interfaces, system interfaces, etc.; physical IP such as cell libraries, memories, etc.; and verification IP. In recent years, EDA companies are starting to offer automatically generated IPs that can be customized by the customer for specific needs, replacing the need to design HW accelerators and similar engines using the standard design methodology. Configurable processors such as ARC (acquired by Synopsys via Virage) and Tensilica (acquired by Cadence) fit well into this business model and it makes sense that these types of IPs be part of EDA companies.
The one piece of IP that EDA companies cannot efficiently provide is open architecture processors, such as CPUs, GPUs and DSPs. Such IPs require a very different set up, including SW development environment, SW components, ecosystem, close customer support throughout the development cycle, robust processor roadmap, and mostly importantly – intimate application-specific knowhow. EDA companies are not structured to run an investment in this manner, which leaves DSP CPU and GPU IP companies better suited to being independent IP suppliers and existing as pure IP plays, structuring the business, R&D investment, customer support etc in the most appropriate way for their customers.
Arvind Shanmugavel, Director of Applications Engineering, Apache Design, Inc.
The semiconductor IP market has undergone several transformations in the past few decades. The hard IP market was first conceived when standard-cell libraries were designed and sold to ease the need for complex transistor-level design for ASICs. General-purpose memories with broad specifications became popular for the ASIC design community. In the last decade, System-on-Chip (SoC) designs have become very popular by integrating various forms of soft and hard IP from different vendors.
With the shrinking time-to-market needs of today’s SoCs, IP is being designed and validated independently by the IP provider. SoC teams do not have the luxury of designing and verifying the functionality of hard and soft IP in-house. IP providers are also offering more complex components such as, I/O interfaces and analog modules that were previously built by the SoC teams. This evolution of the ASIC and SoC industry has enabled a healthy IP market for semiconductors ICs.Brian Bailey
– keeping you covered
If you found this article to be of interest, visit EDA Designline
where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here
to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).