This is a roundup of news or activities in the past few days that may be of interest to people.
Real Intent and DeFacTo Technologies have announced a combined RTL sign-off flow for both CDC and DFT that accelerates the sign-off process. The new flow resulting from their collaboration integrates DeFacTo's SIGNOFF solution with Real Intent's clock domain crossing solution, Meridian CDC, offering a solution for SoC design teams worldwide.
Cadence has helped Yamaha reduce power consumption for its mobile consumer chips with characterization tools that delivered a 10 percent reduction in dynamic power to the clock network. In addition, the Virtuoso Liberate tools enabled Yamaha to characterize these cells automatically by eliminating the need for the user to define the functional description of the cell or specify worst-case conditions.
COMSOL has released new additions to the COMSOL Multiphysics simulation platform.
- Multibody Dynamics Module – analyze the assembly of rigid and flexible bodies.
- Wave Optics Module – analyze electromagnetic wave propagation in optically large structures, such as optical fibers and sensors, bidirectional couplers, plasmonic devices, metamaterials, laser beam propagation, and non-linear optical components.
- Molecular Flow Module – simulate rarefied gas flow in complex CAD geometries of vacuum systems.
- Semiconductor Module – analysis of semiconductor device operations at the fundamental physics level allowing for the modeling of PN junctions, bipolar transistors, MOSFETs, MESFETs, thyristors, and Schottky diodes.
- Electrochemistry Module –user interfaces available for electroanalysis, electrolysis, and electrodialysis.
Red Herring has announced that Jasper Design Automation has been selected as a finalist for Red Herring's Top 100 North America award, a prestigious list honoring the year’s most promising private technology ventures from the North American business region.
Synopsys says that Achronix Semiconductor has successfully used both Synopsys' IC Compiler™ physical design and IC Validator physical verification solutions to sign off its Speedster22i® FPGA – the industry's first system-on-chip (SoC) design using FinFET transistors. Synopsys' IC Compiler physical implementation tool has been enhanced to support correct-by-construction implementation of all FinFET-specific design rules, while the IC Validator physical verification tool used foundry rule decks to enable verification of FinFET-based SoCs and extraction of new FinFET device parameters.
Oasys has announced availability of Oasys RealTime Parallel EC (equivalency checking). Hierarchical support, automatic partitioning and parallel multi-processing technology enable simultaneous verification of sub-blocks, providing performance that scales linearly with the number of processors. The hierarchical top down approach also provides the capacity to perform equivalency checking on an entire chip at once.
Altium has launched an update to Altium Designer 13.2. It has features and enhancements designed to give users better control over their design data and a clearer view throughout the development process. This release provides improved documentation features for PCB designs and significant gains to cost conscious engineering processes.
Forte Design Systems has a new version of its Cynthesizer™ SystemC-based high-level synthesis (HLS) product. The new version includes low power synthesis capabilities, core synthesis algorithms, and a new SystemC integrated development environment (IDE).
Jasper Design Automation has announced the availability of JasperGold® Low Power Verification App (JG-LPV App) which enables users to utilize formal methods for the verification of SOC designs optimized for lower power consumption with multiple voltage and power-management domains. The JG-LPV App reads the RTL description and creates an internal power-aware formal model in accordance with the power partitioning specifications. The new App verifies power optimization structures, power management circuitry, power sequencing, and works with other JasperGold Apps to verify that the power optimizations do not corrupt the original design functionality.
CEA-Leti has announced completion of the HELIOS program. The €8.5 million European Commission project developed a complete design and fabrication supply chain for integrating a photonic layer with a CMOS circuit, using microelectronics fabrication processes. Launched by the European Commission in 2008, HELIOS focused on developing essential building blocks like efficient optical sources, integrated lasers, high-speed modulators and photo-detectors. The project, which had 20 members, also combined and packaged these building blocks to demonstrate complex functions that address a variety of industrial needs. (www.helios-project.eu)
Chip Memory Technology, a new embedded memory technology developer, has emerged from stealth mode to reveal company details and its latest product. CMT’s LogicFlash product is an embedded NVM. Designed for implementation in industry standard CMOS logic processes, LogicFlash requires no extra foundry steps or extra mask layers. This reduces the expense and delay required to qualify and port chip designs that use LogicFlash to new foundries or new processes. Chrontel is currently incorporating LogicFlash into devices being produced in a 130nm standard logic process.
– keeping you covered
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