This blog is the second in the series of industry opinions about various aspects of the IP industry. The first part “What will the IP landscape look like in the future” has been shared quite widely, so it would appear that these are quite popular. Today, the question that was posed to them is about chip makeup. I have heard some people say that IP now consumes 90% of the chip surface and I asked about the accuracy of this figure and how they expect it may change over time.
Michael Munsey, Director of Product Management, Semiconductor Solutions at Dassault Systèmes.
Although there will always be the need for a small amount of new design, it would not be surprising to see 90% of a design or more be made up of IP. With the time to market pressures needed to deliver electronics and the emerging continuous design model, where companies are designing three to four generations of a product continuously, I really do not see this changing in the near term.
John Koeter, Vice President of Marketing, Solutions Group, Synopsys
There are hundreds of IP blocks on a chip and they do cover a significant portion of the chip surface. Embedded memories alone can cover 50 percent of the chip surface. Conceivably a customer could create a chip that is made up of 90 percent third-party IP blocks, however this is very rare. Usually, the hundreds of functions are a mixture of internally designed IP blocks and third-party IP blocks. For the types of IP that Synopsys provides, the ratio between make versus buy is around 50/50.
Susan Peterson, Product Marketing Group Director and Tom Hackett, Senior Product Marketing Manager, Cadence
The general consensus is that an overwhelmingly large percentage of the SoC is made up of standard IP blocks. The pace of new standard protocols has really picked up over the last couple of years, and each one is significantly more complex than the last.
The more standards that become available, and the more people that adopt them, the higher this percentage will become. At some point, and we think that’s now, it’s not just about the number of IP blocks but also the number of standardized subsystems – a group of IP blocks optimized for a particular application, like mobile, networking, or storage, along with the protocols common in these applications.
It’s logical to envision that, in the future, most elements of a SoC will be customized via software, rather than hardware, as devices become increasingly powerful.
From “IP reuse requires both design reuse and verification reuse” Dean Drako, IC Manage - EE Times EDA Designline 4/2/2013
Bernard Murphy, CTO of Atrenta Inc
Depends whether you count only external IP as IP. If so, number seems high. Very large (or maybe very complex) SoCs seem somewhat out of range of any but the largest design/fabbed companies. In these cases, there is a lot of internal IP to leverage, especially communication fabrics, test subsystems, power-management logic, mixed signal, PLLs, etc. Perhaps 70% is a more reasonable asymptote.
Arvind Shanmugavel, Director of Applications Engineering, Apache Design, Inc.
Soft IP including ARM cores and graphics engines combined with hard IP such as memories, analog and serial/parallel interfaces make up a significant portion of an SoC. Mobile application processors today have built-in USB controllers, HDMI display interfaces, and in some cases built-in baseband IP on the same die. The trend in SoC design continues to be in the direction of more IP integration than actual design. A combination of soft and hard IP can easily reach 90% of the chip area over time.
So, it would seem as if there is general agreement if IP includes internal reuse and that if anything these numbers may rise in the future as larger subsystems become supplied as IP. IBS also talks about the number of IP blocks increasing as well. At 65nm a design typically contained 48 IP blocks whereas that has doubled for 32 and 28nm.
Brian Bailey – keeping you covered
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