This year there are eight technical panels at DAC on a wide ranging set of topics covering the areas of new process nodes and technologies, power, verification, security, embedded systems and more. There is sure to be something of interest to just about everyone. All panels will be in room 16AB. In this blog I will take a quick look at each of them for you:
Session 1: Advanced Node Reliability: Are We in Trouble? Tuesday 10:30
I recently did an article in EDN about design for manufacture and yield, and this panel will be all about that subject. Electromigration, electrostatic discharge and many other things can degrade yield and wear out-related defects impact circuit margining and lifetime requirement for critical applications. This panel will discuss the reliability challenges and the best ways for designers, foundries, and EDA vendors to define and develop advanced circuit checks and design sign-off at these advanced nodes.
Session 7: I Blew My Power Budget: Whom Should I Throw Under the Bus? Tuesday 1:30
In the description for this panel they say - During the last phases of the design, or even after first silicon, I discover that the power budget is blown. What can I do at this point? Whom do I blame? What should I do to ensure this does not happen again? The panelists will tell their horror tales. Let’s see who gets thrown under the bus…
My question is how could this scenario ever be allowed to happen when the power savings at this stage are tiny compared to the power options available during early design phases. I guess it will come down to the same answer – leave it to the software guys…
Session 14: Is Security the Next Design Dimension? Tuesday 4:00
When we start talking about the Internet of Things, one subject very quickly comes to the surface – security. But we are seeing security rise as an issue in many other places as well, such as cars, voting machines, medical devices, etc. So how should security be considered during the design phase? It is well-known that incorporating security late in a design is a recipe for disaster , but how should security be prioritized with other design criteria like cost, power, and reliability. The panel will discuss vulnerabilities in integrated circuits and embedded systems and potential solutions to building-in security during design.
Session 21: Disruptive Verification Technologies: Can They Really Make a Difference? Wednesday 9:00
Now this is the must attend panel for 2013. Why? Well because I will be moderating it of course. It will be looking at the verification crisis with the starting proviso that there is no disruptive technology on the horizon. So, what are we to do when most verification teams remain too busy, understaffed and barely able to keep pace with the innovation in design. I am hoping that the panelists will have some far reaching ideas for how we need to solve this problem.
Session 27: Test/Diagnose/Debug: Let the 3D-IC Chaos Begin Wednesday 1:30
2.5D and 3D chips are moving from the lab and into production. The first data are coming from the field. There are many open questions on how to get adequate testing through the manufacturing and assembly process to ensure the economic viability of the 3D-IC. This panel will debate which are the most critical open issues related to the test, diagnosis and debug processes and suggest solutions and metrics.
Session 34: EDA: Meet Analytics; Analytics: Meet EDA Wednesday 4:00
This is a second verification focused panel for this year and this one is looking at the hugs amount of data that EDA tools create. The premise is that analytics can be helpful in sizing the problem, assessing progress, and improving process. However, beyond familiar coverage metrics, this is not the case today. This panel considers statistical analysis, data mining, machine learning, and other analytic methods to gain more insight into verification – and whether the analytics approach can extend to other SoC design areas.
Session 41: Barriers to the Internet of Things: Embedded Software, Security, Cost, Power? Thursday 9:00
The Internet of Things is being hyped as the next big thing. All kinds of everyday products will have intelligence and a network connection will be controlled by mobile devices and will send data to the cloud. For example, your toaster or your glasses can talk to the cloud. That all sounds great, but what will be the barriers to growth: embedded software, security, cost or power? Or, is it the unstoppable next wave?
Session 47: Analog Design with FinFETs: “The Gods Must be Crazy!” Thursday 1:30
FinFET devices have emerged as the winner for process nodes beyond 20nm. The advantages are too compelling to ignore. However what’s great for SoC is a real challenge for analog. With sub-threshold currents near zero and virtually no bias control capability, suddenly the analog designer will have to throw out the old schematics and really start to rethink the problem. The big question: How quickly will mainstream analog design find its way into FinFET-driven logic processes?
Session 54: Cyber-Physical System Software: Emperor’s New Clothes or Not? Thursday 3:30
Have you heard the term “cyber-physical systems (CPS)”? I must admit it is a new one to me but it was introduced in order to express a view on systems—such as cars, buildings and the smart grid—which is wider than that on traditional embedded systems. This widening includes the modeling of the physical environment and the linking of embedded systems through the use of network-based communications. One question about cyber-physical systems pops up immediately: What is new for cyber-physical systems? More in particular: What is new for cyber-physical system software?Brian Bailey
– keeping you covered
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