This is a roundup of news or activities in the past few days that may be of interest to people.
Imec and Renesas Electronics have entered into a strategic research collaboration at Holst Centre. Together, the companies will collaborate to enhance ultra-low power (ULP) wireless technologies for short range communication, targeting sensor networks for automotive and industrial purposes. Renesas will work to jointly develop multi-standard radio solutions for small battery-operated or harvested wireless handheld devices. Imec’s ULP radios are compliant with state-of-the-art wireless standards, such as Bluetooth Low Energy (2.4GHz band) and ZigBee (2.4GHz band).
Berkeley Design Automation has announced Analog Characterization Environment (ACE™)—a system to ensure nanometer-scale analog and mixed-signal circuits meet rigorous design performance requirements. ACE provides a user interface to setup, launch, monitor, report, and visually analyze circuit characterization runs. ACE supports leading SPICE-compatible simulators, standard measure formats, and operates both as a standalone tool and integrated with the industry’s leading analog design environment. The user interface has nearly identical corner, sweep, and Monte Carlo set-ups. ACE reads corner information from the process design kit (PDK) or the user’s analog design environment, and it supports measures in existing industry standard formats for facilitating specification analysis.
Real Intent says that its revenue in the first half of fiscal 2013 increased more than 70-percent compared to the last half of fiscal 2012, and the company is on track for annual growth of more than 100-percent by the end of 2013. In addition, Real Intent’s customer list grew by more than 20-percent, which includes major semiconductor companies in storage, computing, networking, communications and consumer electronics industries.
Samsung has announced a 45nm embedded flash (“eFlash”) logic process development. They have implemented the new process into the smart card test chip. The test chip has random access time to read memory that is 50 percent faster and the power efficiency is enhanced by 25 percent over previous products built on the 80nm eFlash logic process.
Mentor Graphics and Tezzaron Semiconductor have announced a collaboration to integrate the Mentor Calibre 3DSTACK product into Tezzaron’s 3D-IC offerings. The new integration will focus on verification of die-to-die interactions in 2.5D and 3D stacked die configurations by verifying individual dies in the usual manner, while verifying die-to-die interfaces in a separate procedure with specialized automation features.
Oasys Design Systems has now made Floorplan Compiler available as a separate tool in the Oasys RealTime suite of physical RTL exploration and synthesis tools. Synthesis engineers, architects and RTL designers can now create a floorplan directly from the RTL that is aware of the designs dataflow and also meets timing, power, area and congestion constraints. The resulting floorplan can then be fed forward as initial guidance to physical design teams.
Aldec has launched Spec-TRACER, a requirements lifecycle management solution for use in safety-critical industries in which certification standards exist; such as DO-254 for avionics, ISO 26262 for automotive, IEC 61508/61511 for industrial and IEC 61513 for nuclear. Spec-TRACER helps organizations manage, control and track requirements throughout the entire FPGA/ASIC development lifecycle. It does this by streamlining and automating the requirements engineering process such as capture, traceability, requirements versions tracking, results management and reporting.
Imec and GlobalFoundries have expanded joint development efforts to advance STT-MRAM (spin-transfer torque magnetoresistive random access memory) technology. STT-MRAM technology is a promising high-density alternative to existing memory technologies, like SRAM and DRAM. Together, imec and the program members aim to explore the potential of STT-MRAM, including performance below 1nanosecond (ns) and scalability beyond 10 nanometers (nm) for embedded and standalone applications.
Cypress Semiconductor has introduced PSoC Designer 5.4, a new version of its Integrated Design Environment (IDE) for the PSoC 1 Programmable System-on-Chip architecture. The new version includes over 40 new or enhanced User Modules, which are free “Virtual Chips,” represented by an icon, that are used to integrate multiple ICs and system interfaces into a single PSoC device. Version 5.4 also offers multiple new features including an Auto-Complete feature that automatically suggests variables, functions, and keywords as users type. It allows customers to create their own User Modules, with control over the hardware, firmware, and graphical user interface.
The Silicon Integration Initiative (Si2) announced today that several leading semiconductor and EDA companies have voiced their commitment to adopt Si2’s OpenDFM standard version 2.0. The OpenDFM standard describes an open, high-level language that can generate popular verification runsets for use in any major EDA design for manufacturability (DFM) verification tool. OpenDFM allows designers to maintain one EDA-tool independent source for DFM checks.
The 50th Design Automation Conference (DAC) will feature a day of training tracks to keep designers updated on the latest techniques. Four tracks of training will be held on Thursday, June 6th, 2013. The four tracks are SystemVerilog design, SystemVerilog verification, ARM accredited engineering program and ESL and SystemC.
Imperas Software has released its 2nd generation virtual platform development and multicore software design kit product offerings. The new Developer range and Multicore Software Development Kit products utilize a simulator that leverages a Just-In-Time code morphing mechanism. Imperas’ ToolMorphing technology extends this mechanism to generate tool and model code together. Each of the Developer products include: iGen™ a model generator, the Imperas Model library of 100+ cpu model variants and the Imperas simulator.
Mentor Graphics has teamed with OpSIS and Lumerical Solutions to develop a complete EDA-style, full flow process design kit (PDK) for the OpSIS IME (Institute of Microelectronics) silicon photonics process. The prospect of integrating a silicon photonics process with silicon-based electronics would allow adding the driver and control electronics on the same chip, greatly reducing packaging complexity and cost. Adding a photonic layer and interconnects also holds the promise of solving speed bottlenecks in future computing and chip platforms.
Avery Design Systems has released its eMMC and SD verification IPs. eMMC-Xactor supports eMMC 4.5.1 and draft 5.0 standards work by JEDEC targeting high performance embedded flash memory systems. SD-Xactor supports SD/SDIO 4.0 for high performance memory cards, systems, and IO peripherals.
Worldwide semiconductor revenues decreased by 2.2% year over year to $295 billion in 2012, according to the latest version of the International Data Corporation (IDC) Semiconductor Application Forecaster (SAF). The industry witnessed a slowdown during the second half of 2012 on weak consumer spending across PCs, mobile phones, and digital televisions (DTV), as well as in the Industrial and other market segments. The European economic crises and a slowdown in China also had an impact on global demand while the lackluster launch of Windows 8 failed to stimulate PC sales and turn the tide. Meanwhile, competitive suppliers from China continued to pressure average selling prices, dragging down overall revenue growth. IDC expects the semiconductor market to return to growth in 2013 with revenues forecast to increase by 3.5% this year.
North America-based manufacturers of semiconductor equipment posted $1.17 billion in orders worldwide in April 2013 (three-month average basis) and a book-to-bill ratio of 1.08, according to the April EMDS Book-to-Bill Report published today by SEMI. The bookings figure is 6.4 percent higher than the final March 2013 level of $1.10 billion, and is 26.8 percent lower than the April 2012 order level of $1.60 billion.
Cadence has announced that TSMC has certified the new Cadence Tempus Timing Signoff Solution at 20 nanometers. The certification means the Cadence Tempus Timing Signoff Solution passes TSMC’s EDA tool certification to enable customers to achieve accuracy required for advanced technologies. More information about Tempus can be found here.Brian Bailey
– keeping you covered
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