The traditional DRC verification flow used by custom layout designers simply can't provide the needed level of productivity when debugging DRC results at advanced nodes.
and verifying multi-input voltage designs, designers must ensure the
layout complies with metal spacing design rules that are dependent on
the voltage drop values on the signal nets. For example, a typical
voltage drop rule might require that minimum spacing between metal lines
must be x wherever the voltage difference between metal lines is higher
than V (volt), otherwise the spacing must be y. The corresponding
voltage drop check (VD-DRC) must ensure that these conditions are
The inputs for our VD-DRC check are the maximum
(MaxV) and minimum (MinV) voltage values on the nets. The DRC engine
examines the voltage differences between the metal lines, and flags any
VD-DRC violations. For a design to pass the VD-DRC checks, designers
must know the MaxV and MinV voltage values on the nets, and attach these
voltage values to the nets in the layout.
design techniques, the voltage values can be provided using either text
on the geometries or marker layers. This information is then included in
the GDSII that is passed to the verification tool. This technique is
highly inefficient, as it requires designers to manually insert text on
each of the nets, or add marker layers, both of which are time-consuming
and prone to error. Also, designers are often not knowledgeable about
the voltage values that should be present on the nets, which can lead to
inaccurate values being used.
Using the Calibre RealTime/Laker
integration (Figure 2), designers complete the schematics for their
design, and then run simulations on the schematics to generate a voltage
table containing the MaxV and MinV voltage values present on each of
the nets in the design. The voltage values are stored in the OpenAccess
(OA) database in a view called the “constraint” view. When designers
edit their layout design, Calibre RealTime reads the voltage values
present on the nets in the layout from the OA constraint view, and
processes this information in association with the layout geometries to
generate the appropriate VD-DRC results.
Figure 2: VD-DRC flow in Synopsys Laker OpenAccess with Calibre RealTime.
new flow requires that the net names in the schematic and layout views
match so that, for a given net in the schematic, Calibre RealTime can
find the corresponding net in the layout and apply the appropriate
voltage values read from the constraint view. Designers can use the
schematic-driven layout capability present in the design tool to ensure
that there is a one-to-one correspondence for the net names between the
schematic and layout views.