Did we just witness the first of what will be an increasing number of events that signify the slowing or even the end of Moore's Law?
Have we just witnessed the first of what will be an increasing number of events that signify the slowing or even the end of Moore's Law? Moore's Law is the self-fulfilling prophecy that transistor counts on integrated circuits would double every two years, named after Gordon Moore, co-founder and past CEO and chairman of Intel, who himself thought his "law" would last at best for about a decade until 1975.
The more recent event I refer to was the acknowledgement by SanDisk Corp. (Milpitas, Calif.) that its 1Y generation of NAND flash nonvolatile memory would manufactured using 19-nm minimum geometry; the same as its 1X generation (see SanDisk's 1Y flash stays at 19-nm).
Given that the 1X-nm term was originally coined to denote a manufacturing process node somewhere between 10- and 19-nm it is clear that 1Y and 1Z imply nodes also between 10- and 19-nm but different to the 1X node.
To judge from an Intel depiction of the transition to 3-D NAND that company also agrees that there are a couple of nodes left that can exploit the charge storage principle of NAND flash at about 15-nm and 10-nm (see Intel outlines 3-D NAND transition).
So what happened at SanDisk and, by implication Toshiba, its manufacturing partner?
One possibility is that SanDisk stared into the abyss of triple or quadruple patterning using masks and immersion lithography to define minimum geometries of 15-nm. While the technical possibility of getting to 15 or even 10-nm with multiple patterning is well understood there have long been concerns about the extra dwell time on machines, the complexity of additional process steps and the impact on yield. Instead SanDisk found a way to improve the memory cell through design — reducing the area by about 25 percent – and without the scaling the geometry.
Some might argue that the die area saving achieved is equivalent to a process node move, and that as Moore's talked about the number of transistors per IC his law is not dependent on a reducing minimum geometries.
I think that most will see that this runs against the "spirit" of Moore's Law. We have already seen the harbinger of its breakdown with the introduction of such terms as 1X, 1Y and 1Z serving to confuse node nomenclature in memory. In the logic world we have similar confusion with FinFET processes being based on 20-nm back-end of line processes but labeled at 16-nm and 14-nm. But progress has continued.
However, when it is no longer economic to move to the next manufacturing process node that looks like a Moore's Law failure to me.
It remains to be seen what will happen at the 1Z node and Moore's Law for NAND flash may continue a little longer at Samsung, Intel and others. However, it seems like there could be similar "epic fails" to come in both memory and logic. It all depends whether this is a blip awaiting the resumption of progress with extreme ultraviolet (EUV) lithography or whether with or without EUV the miniaturization of circuits has just become too expensive and design progress will win out over geometry from now on.
I view Moore's law as a business phenomenon as much as a technology phenomenon. It basically said that at a certain sustainable capital and R&D investment rate, the industry kept doubling the transistor budget every 18 months. Unfortunately, lately the equipment got so exotic and expensive that the capital investment required to stay on the Moore's curve is not justifiable--except perhaps to the largest players with deepest pockets.
As well as being an observation there was a forward-looking element to Moore's comments, which were based not so much on the laws of physics but on the nature of economics.
To quote from the 1965 Electronics article: "Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years."
In the article Moore went on to speculate how many transistors it would be economic to integrate monolithically in 1975, which at that time was ten years' hence.
So you are right, Moore did not say scaling would continue into atomic dimensions, but what he stated was more than just an observation on historical levels of integration.
"Well it was a prophecy when made by Gordon Moore in 1965."
You mean an observation, not a prophecy. His was not a law, it had no rigorous physics behind it, it was just that at that time scaling seemed quite possible in the near future. I'm sure Moore himself would never have said scaling would continue into atomic dimensions, he was not that stupid.
Peter I think you are spot on and it's surprising mainstream press has not picked up on this
For logic is it clear based on Tawain semi offering 20 and 16 does not provide historical die size shrink or a lower cost per transistor and an ending of moores law.
28 to 20 only provided a die size shink of ~35% (when buying 4 layers of metal double patterning...typical for many SOC) and
20 to 16nm has ZERO die size reduction at higher wafer cost (a non-starter for most markets)
Well it was a prophecy when made by Gordon Moore in 1965.
And once made I feel it set a level of expectation that the industry has tried hard to meet. Company such as Intel, forward plan based on the expectation of a two year cycle.
This and similar planning at other companies in turn set the agenda for the semiconductor equipment companies, which in turn affected what technologies become available when.
The general effect was, for the industry players' mutual convenience, the tie the industry in to a roughly two-year cycle. It was also reflected in such things as the International Technology Roadmap for Semiconductors (ITRS) and the predictions made therein.
That is why i believe the prophecy has been largely self-fulfilling ...up until now....
Why in the world would you call Moore's Law a self-fulfilling prophecy. It is neither, rather being a historical trend on how fast people manage to build new technologies that has had surprisingly significant predictive power. The first time that physics and fabrication technology come into it is (perhaps) when people can't keep up the rate of innovation.
"Instead SanDisk found a way to improve the memory cell through design — reducing the area by about 25 percent – and without the scaling the geometry." That is a wrong statement because the memory-cell bitline pitch scales down from 26nm to 19.5nm while the wordline pitch remains at 19nm (see press release: http://www.sandisk.com/about-sandisk/press-room/press-releases/2013/sandisk-advances-its-industry-leading-manufacturing-technology/ ). So the core cell size reduction is 25%, and the total chip size reduction is about 20% when periphery is included for a 64Gb 2-bit-per-cell chip.
I'm not arguing how long Moore's Law will hold in the future. 1Y could be considered as half a node from 1X. Considering 1x just came out last year, the scaling trend is still pretty impressive. You can also consider 2X to 1Y as a full generation node, and that took less than three years for SanDisk/Toshiba to develop.
Well the general consensus I have heard from the likes of IMEC, SanDisk, Intel is that 3-D NAND replaces 2-D NAND and scales the technology in the vertical direction. Not so much a 1M-nm generation as a 4M-nm generation...
And when you hit a limit in the z direction due to the ability to coat the depth of the high aspect ratio through-silicon-wire holes you return to lateral scaling with ReRAM...And by then a more complete understanding of the physics of this resisitve systems may have been achieved.