Did we just witness the first of what will be an increasing number of events that signify the slowing or even the end of Moore's Law?
Have we just witnessed the first of what will be an increasing number of events that signify the slowing or even the end of Moore's Law? Moore's Law is the self-fulfilling prophecy that transistor counts on integrated circuits would double every two years, named after Gordon Moore, co-founder and past CEO and chairman of Intel, who himself thought his "law" would last at best for about a decade until 1975.
The more recent event I refer to was the acknowledgement by SanDisk Corp. (Milpitas, Calif.) that its 1Y generation of NAND flash nonvolatile memory would manufactured using 19-nm minimum geometry; the same as its 1X generation (see SanDisk's 1Y flash stays at 19-nm).
Given that the 1X-nm term was originally coined to denote a manufacturing process node somewhere between 10- and 19-nm it is clear that 1Y and 1Z imply nodes also between 10- and 19-nm but different to the 1X node.
To judge from an Intel depiction of the transition to 3-D NAND that company also agrees that there are a couple of nodes left that can exploit the charge storage principle of NAND flash at about 15-nm and 10-nm (see Intel outlines 3-D NAND transition).
So what happened at SanDisk and, by implication Toshiba, its manufacturing partner?
One possibility is that SanDisk stared into the abyss of triple or quadruple patterning using masks and immersion lithography to define minimum geometries of 15-nm. While the technical possibility of getting to 15 or even 10-nm with multiple patterning is well understood there have long been concerns about the extra dwell time on machines, the complexity of additional process steps and the impact on yield. Instead SanDisk found a way to improve the memory cell through design — reducing the area by about 25 percent – and without the scaling the geometry.
Some might argue that the die area saving achieved is equivalent to a process node move, and that as Moore's talked about the number of transistors per IC his law is not dependent on a reducing minimum geometries.
I think that most will see that this runs against the "spirit" of Moore's Law. We have already seen the harbinger of its breakdown with the introduction of such terms as 1X, 1Y and 1Z serving to confuse node nomenclature in memory. In the logic world we have similar confusion with FinFET processes being based on 20-nm back-end of line processes but labeled at 16-nm and 14-nm. But progress has continued.
However, when it is no longer economic to move to the next manufacturing process node that looks like a Moore's Law failure to me.
It remains to be seen what will happen at the 1Z node and Moore's Law for NAND flash may continue a little longer at Samsung, Intel and others. However, it seems like there could be similar "epic fails" to come in both memory and logic. It all depends whether this is a blip awaiting the resumption of progress with extreme ultraviolet (EUV) lithography or whether with or without EUV the miniaturization of circuits has just become too expensive and design progress will win out over geometry from now on.
Related links and articles:
Broadcom: Time to prepare for the end of Moore’s Law
TSMC starts FinFETs in 2013, tries EUV at 10 nm
TSMC expected to begin 20-nm line early