Have we just witnessed the first of what will be an increasing number of events that signify the slowing or even the end of Moore's Law? Moore's Law is the self-fulfilling prophecy that transistor counts on integrated circuits would double every two years, named after Gordon Moore, co-founder and past CEO and chairman of Intel, who himself thought his "law" would last at best for about a decade until 1975.
The more recent event I refer to was the acknowledgement by SanDisk Corp. (Milpitas, Calif.) that its 1Y generation of NAND flash nonvolatile memory would manufactured using 19-nm minimum geometry; the same as its 1X generation (see SanDisk's 1Y flash stays at 19-nm).
Given that the 1X-nm term was originally coined to denote a manufacturing process node somewhere between 10- and 19-nm it is clear that 1Y and 1Z imply nodes also between 10- and 19-nm but different to the 1X node.
To judge from an Intel depiction of the transition to 3-D NAND that company also agrees that there are a couple of nodes left that can exploit the charge storage principle of NAND flash at about 15-nm and 10-nm (see Intel outlines 3-D NAND transition).
So what happened at SanDisk and, by implication Toshiba, its manufacturing partner?
One possibility is that SanDisk stared into the abyss of triple or quadruple patterning using masks and immersion lithography to define minimum geometries of 15-nm. While the technical possibility of getting to 15 or even 10-nm with multiple patterning is well understood there have long been concerns about the extra dwell time on machines, the complexity of additional process steps and the impact on yield. Instead SanDisk found a way to improve the memory cell through design — reducing the area by about 25 percent – and without the scaling the geometry.
Some might argue that the die area saving achieved is equivalent to a process node move, and that as Moore's talked about the number of transistors per IC his law is not dependent on a reducing minimum geometries.
I think that most will see that this runs against the "spirit" of Moore's Law. We have already seen the harbinger of its breakdown with the introduction of such terms as 1X, 1Y and 1Z serving to confuse node nomenclature in memory. In the logic world we have similar confusion with FinFET processes being based on 20-nm back-end of line processes but labeled at 16-nm and 14-nm. But progress has continued.
However, when it is no longer economic to move to the next manufacturing process node that looks like a Moore's Law failure to me.
It remains to be seen what will happen at the 1Z node and Moore's Law for NAND flash may continue a little longer at Samsung, Intel and others. However, it seems like there could be similar "epic fails" to come in both memory and logic. It all depends whether this is a blip awaiting the resumption of progress with extreme ultraviolet (EUV) lithography or whether with or without EUV the miniaturization of circuits has just become too expensive and design progress will win out over geometry from now on.
I think in the NAND market you are getting the first indications of working ReRAM. If vendors are moving to a completely new architecture/technology, how hard are they going to push on the current technology?
I think what we might want to call the 1M generation should be added to the list. M for Multi-Chip Package (MCP) where chip stacking, with Through Silicon Vias (TSVs) is used to achieve the required doubling of transistor/memory device density and is likely to play a significant role at about the 19-20nm node. In that way, take your pick for MCP or 3D monolithic, a constant chip footprint (area) will be meet the prediction of Moore's Law independent of the lithographic node.
Well for NAND, the quadruple patterning to 10 nm would not have been more lithography/masks but certainly more process steps. Hynix did ~15 nm at IEDM two years ago. It would have made more sense to do this for both the 1Y and 1Z nodes, with both 1Y and 1Z closer to 10 nm to offset the potential doubling of costs with quadruple compared to double patterning. Now that 1Y is still 19 nm, it doesn't make much sense. Also possible, too close to 10 nm is too big a risk with S-D tunneling.
Peter, I think you have it right. Of course this is all about cost. The profit margins for commodity NAND chips simply are not high enough to justify the costs required to go to a smaller node right now. So the "more than Moore" design optimization was the best/only economical choice. At this point no one is counting on EUV litho coming to the rescue any time soon.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.