This is a roundup of news or activities in the past few days that may be of interest to people.
Product and IP related news
Berkeley Design Automation has announced Analog FastSPICE Mega (AFS Mega) silicon-accurate circuit simulator for memories and other mega-scale array-based circuits such as CMOS image sensors. This extends the company’s foundry-certified Analog FastSPICE™ Platform with mega-scale array verification and characterization into FinFET-based process nodes. Mega-scale arrays dominate the silicon area in most nanometer-scale integrated circuits (ICs) including system-on-chip ICs with embedded SRAM, memory ICs, and CMOS image sensors (CIS). They also said that TSMC is using this for memory IP verification. Memory IP circuits implemented in 16-nm and smaller FinFET-based process nodes must meet stringent performance targets while requiring six-sigma bit cell yield to meet cost and power targets.
ATopTech has a new release AP 13.02 (release 2.0) for its AprisaTM and ApogeeTM tools. The release includes certified TSMC 16nm FinFET v. 0.1 support with color-aware double patterning technology (DPT) routing and FinFET-aware placement, a statistical on-chip variation (SOCV) methodology, physical-aware scope-based sign-off (PASS) timing ECO and a virtual flat methodology.
Atrenta is collaborating with Mentor Graphics to enable accurate, signoff quality power estimation at the register transfer level (RTL) for the entire system on chip (SoC) device. The project aims to radically improve SoC design efficiency by facilitating RTL power estimation for designs in excess of 50 million gates, running actual software scenarios over hundreds of millions cycles, resulting in large simulation data sets in excess of 10Gbytes. The collaboration has resulted in an interface between the Mentor Veloce2 emulator and Atrenta’s SpyGlass Power RTL power estimation tool.
Forte Design Systems and CircuitSutra have announced that they will partner to provide design services throughout India to support the growing system-on-chip (SoC) market. As part of the agreement, Forte and CircuitSutra will co-develop ARM AMBA AXI and OCP-IP models compatible with Forte’s Cynthesizer SystemC high-level synthesis (HLS). They will work together to deliver onsite consulting and training for Cynthesizer users in India.
Carbon Design Systems is supporting the latest ARM technology, and will create and deliver virtual models for the ARM® Cortex®-A57 and Cortex-A53 processors, as well as CoreLink™ CCN-504 system intellectual property (IP).
Target Compiler Technologies has announced enhancements which collectively move the company into the intellectual property (IP) subsystem domain. MP Designer is a tool-suite that helps engineers balance both software and hardware decisions for multicore subsystems. They have increased the architectural breadth of Target’s IP Designer™ tool-suite for the design of application-specific processors (ASIPs), coupled with an increase in scope in IP Designer’s modeling capability. Designers can now model advanced communication and memory interfaces for their ASIPs.
Vayavya Labs has announced SOCX-Verifier a software-driven verification tool that automatically generates verification test software and relevant test-bench components from a system-level scenario specification. With SOCX-Verifier, SoC designers can now bridge and thus greatly accelerate the arduous hardware-software co-design process.
Khalifa University has announced an agreement with Circuits Multi Projets (CMP) where Khalifa University will collect projects from universities, research laboratories and companies based in the UAE and send them to CMP for manufacturing. These projects will include prototypes for new integrated circuits and MEMS. Khalifa University will also be able to submit designs by its students and faculty for manufacturing. CMP will offer manufacturing in a variety of processes including advanced processes provided by STMicroelectronics.
Kozio has announced the release of a Verification and Test OS (VTOS™) package for the 4th Generation Intel Core processor family. VTOS combines over 300 sub-system tests, scripting, in-system programming and command line access to provide a solution for embedded hardware design verification and test.
Cortus has announced that its Cortus processor cores have been chosen by Microsemi Corporation for a new mixed signal system-on-chip SoC platform for industrial applications. Cortus processor cores are designed to meet the needs of the emerging wave of smart applications. The small silicon area of the cores means that they have ultra-low power and are well suited for use with mixed signal technologies typically used for modern sensors.
Plunify utilizes the cloud as a platform to allows FPGA designers to accelerate chip design workflows.They have announced availability of Altera Quartus II for designing with Stratix, Cyclone and Arria devices. The new relationship with Altera marks the production availability of Plunify's cloud based solution for FPGA design.
Agilent has announced two reference libraries for SystemVue for communications and aerospace/defense systems design. The Global Navigation Satellite System baseband verification and Digital Modem libraries allow system designers and algorithmic researchers to bring instrument-grade standards references into design simulation early in the R&D process. Satellite and communications systems can now be verified under a variety of realistic impaired conditions, before baseband or RF hardware is available, enabling faster deployment of high-performance systems.
Ausdia has introduced an add-on product for its Timevision timing constraints development, verification and management solution. Timevision-CDC checks the safety of asynchronous clock domain crossings while simultaneously leveraging and verifying the SDC (Synopsys design constraint) file that specifies the asynchronous relationships.
Blue Pearl Software has a customized version of its software suite that implements the Xilinx design methodology checklist. Xilinx users can now verify their RTL for issues that are traditionally found late in the design cycle.
IPextreme has welcomed Adapt-IP as the newest member of its Constellations initiative, which brings together like-minded companies to advance the state of the global semiconductor intellectual property (IP) ecosystem. Adapt-IP marks the fourth new addition this year to the rapidly expanding Constellations program.
Earlier this week, I published an article about the new AMBA 5 Coherent Hub Interface (CHI). Now, Mentor Graphics has announced that cache coherent interconnect subsystem verification has been added to the Questa® and Veloce® platforms. Engineering teams designing high-performance, distributed computing systems with ARM’s AMBA 5 CHI specification can verify that the interconnect subsystems achieve maximum system-level performance and the distributed cache memories are coherent.
Cadence is also offering verification IP (VIP) that simplifies functional verification, provides interconnect performance analysis, and creates verification test suites for multi-core interconnects.Brian Bailey
– keeping you covered
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