This is a roundup of news or activities in the past few days that may be of interest to people.
Back end and foundry related news
Mentor Graphics have announced that Calibre nmDRC and Calibre nmLVS rule decks for Samsung’s 14nm IC manufacturing processes have been significantly improved since first release. Joint efforts have resulted in a 50% better performance over the previous release for the Calibre nmDRC design kit.
Staying with Mentor for a moment, they have collaborated with Globalfoundries to deliver 20nm design kits for the Olympus-SoC netlist-to-GDS platform. The design kit enables mutual customers to achieve the best performance, power and area with faster design closure times. The Olympus-SoC router has its own native coloring engine along with verification and conflict resolution engines that detect and automatically fix double patterning violations. Expanded features include DP-aware pattern matching, coloring-aware pin access, pre-coloring of critical nets, and DP-aware placement.
In fact, Globalfoundries will unveil what they claim to be a comprehensive set of certified design flows to support its most advanced manufacturing processes at DAC. The flows, jointly developed with the leading EDA providers, offer robust support for implementing designs in the company’s 20nm low power process and its leading-edge 14nm-XM FinFET process. In addition, a set of certified design flows to support 2.5D IC product development will be announced.
In conjunction with the launch of the ARM Cortex-A12 processor, ARM and Globalfoundries have announced new power, performance and cost-optimized POP™ technology offerings for the ARM Cortex-A12 and Cortex-A7 processors for GF 28nm-SLP High-K Metal Gate (HKMG) process technology.
Moving to a different fab, Synopsys has announced the availability of a design implementation solution for the Samsung 14LPE FinFET process. The solution includes new fast-field-solver technologies to model the effect of 3-D structures for parasitic extraction, accurate high-performance models for device simulation, and comprehensive support for new rules for physical design implementation. The silicon-validated solution developed under exclusive engineering collaboration accelerates adoption of the new 3-D FinFET devices for Samsung's 14-nanometer (nm) process geometry.Brian Bailey
– keeping you covered
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