Arasan, Cadence, IBM, IEEE, Intellitech, Mentor, Real Intent, Toshiba, UMC and X-FAB made the lineup today. See here for their news...
This is a roundup of news and activities over the past week that may be of interest to people.
Arasan Chip Systems has announced the release of its SSIC Adapter IP, supporting the USB 3.0 specification for USB Superspeed Inter-Chip (SSIC). The SSIC IP provides low power, high speed chip to chip interconnect which leverages existing investments in USB software and system investments. High performance and reduced power are achieved by using the MIPI M-PHY as the physical layer interface which lowers the active power and idle power. The SSIC adapter layer IP is optimized for power, area, and EMI robustness for embedded inter-chip interfaces.
Toshiba has an MROM cell achieved by adopting a multi-level-cell structure. MROM's main role is to store the boot loader or firmware. A multi-bit cell uses twice the area of a standard single level cell but triples the current characteristic of the cell without any change in the memory capacity per area. It reduces the influence of the variation in fabrication by 42%. Developed using a 40nm process and aims to ship in 2014.
Cadence has completed the acquisition of the IP business of Poland-based Evatronix, SA SKA. Evatronix has a silicon-proven IP portfolio, which includes certified USB 2.0/3.0, MIPI, display, and storage controllers.
United Microelectronics Corporation (UMC) will join the IBM Technology Development Alliances as a participant in the group’s development of 10nm CMOS process technology. This expands upon their 2012 agreements concerning prior nodes, including 14nm FinFET.
X-FAB Silicon Foundries has enhanced the XP018 process with multiple options to lower chip costs for high-performance analog applications such as audio, sensor interface and 5V-environment power management applications. These options make the XP018 ideal for cost-sensitive consumer applications that require analog integration in 180nm technologies.
Real Intent has announced the Version 5.0 release of its Meridian CDC product for comprehensive clock domain crossing analysis. This new software release adds enhanced speed, analysis and SystemVerilog language support. It also has a hierarchical flow that supports partitioned analysis without waivers or sacrifice of full-chip precision for sign-off of giga-scale designs.
IEEE has announced IEEE 1149.1™-2013 “Standard for Test Access Port and Boundary-Scan Architecture.” IEEE 1149.1-2013—commonly known in the industry as “JTAG,” for “Joint Test Action Group”—is intended to dramatically lower electronics industry costs by enabling test re-use across all phases of the integrated circuit (IC) lifecycle via vendor-independent, hierarchical test languages. The revision allows critical domain expertise for intellectual property (IP) to be transferred in a computer-readable format. It specifies a new hierarchical Procedural Definition Language (PDL)—a standard test language based on Tcl, and hierarchical extensions to the original Boundary Scan Description Language (BSDL) to describe on-chip IP test data registers. Eight new optional IC instructions are included.
Intellitech Corporation has announced support for accessing "Silicon Instruments" through the new IEEE 1149.1-2013 JTAG standard. Examples of Silicon Instruments are: Memory BIST, I/O BIST, Logic BIST, SERDES PRBS, voltage droop monitors and temperature monitors. The hierarchical extensions to 1149.1 Boundary Scan Description Language (BSDL) allows self-contained Silicon Instrument descriptions to be supplied by the instrument provider in a new 'package' file format. These descriptions can then be instantiated and connected together via new capabilities of 1149.1-2013 that use the IEEE 1500 "Standard for Embedded Core Test" standard.
Mentor Graphics has announced MIPI-protocol verification IP (VIP) for use with their latest-generation Veloce® hardware emulation platform. The MIPI VIP enables the use of stimuli generated by modern simulation testbenches, including SystemVerilog/UVM, and SystemC-based environments, and applies them to a MIPI-based, design-under-test (DUT) running in the Veloce emulator. Since the connection between the testbench and the VIP is at a transaction-level rather than signal interface, a high level of performance is delivered. The new VIP supports users of the MIPI camera and display-based protocols, CSI and DSI.Brian Bailey
– keeping you covered
If you found this article to be of interest, visit EDA Designline
where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here
to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).