In the semiconductor field, small usually means the biggest chips built using the latest process technology. It implies the cutting edge. It is where your products want to be if they are to be considered products that the top tier SoC companies will be buying. But let’s take a step back for a minute. One of the big problems for the EDA industry is that there are fewer of those companies and at each node, costs take another significant step up meaning that we are likely to see those numbers continue to shrink. But there are still huge numbers of new chips being designed using larger geometries, older process technologies and sizes that are far from the biggest possible. These BIG chips are a much larger market and the companies designing those chips are making many of their own technological leaps forward.
And thus it was that I talked to Dermott Lynch, VP of Sales at Silicon Frontline. First of all, don’t let the title fool you. This is a guy who knows his stuff, not just how to make a deal. Silicon Frontline had two new tools that they announced just before DAC. The first product is called Ethan. It is a thermal simulation product but not for those small chips. This is about BIG chips and really big devices. In fact it is targeting power transistors and other components associated with the power supply. The mechanics of these devices is a little different from logic transistors. There you have switching currents that translate into heat, but while not switching they just have a steady leakage current. Power transistors are meant to conduct power and many of the components are defined in terms of their efficiency to perform that task. They consume power all the time as do the tracks that feed that power around the chip or to the package.
Many of these devices also have to be cognizant of their environment. For example, electronics on or around an automobile engine block will be getting lots of heat from the engine and this can make a huge difference to the way in which the electronics operates.
The second product is called ESRA and it is targeting electrostatic discharge. Dermott told me that 25% of chip failures are caused by these discharges and so making sure your chip is designed to handle them is important to overall yield. ESRA is a layout verification tool that will analyze the common events, model them and simulates them on the device. Common models include CDM (charged device model), MM (machine model) and HBM (human body model).
Now, after we had talked about the products, I asked Dermott about DAC and his impressions of it. Almost everyone I have spoken to has said how good DAC was for them. Dermott had some data to back it up. He told me that in the five or six DACs that they have attended they never went away with a company committed to an evaluation. This year they had two lined up by the end of the show and another seven or eight looking to start soon. That is results! That is what is important and not the numbers!Brian Bailey
– keeping you covered
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