Here's what you need to know about circuit reliability as advanced processes raise new issues.
Coming back from the Design Automation Conference (DAC), my head is swimming with acronyms. In fact, most people refer to the conference by its acronym instead of its full name. I believe as long as there are engineers and we continue to “engineer,” we will continue to create new acronyms. That is probably a tautology.
One of the themes pervasive at this year’s DAC was circuit reliability, or circuit robustness against electrical failure. There were multiple venues (panel discussions, booth presentations, white papers, etc.) and they were replete with scary potential sources of circuit failure and, of course, their requisite acronyms such as Electrostatic Discharge (ESD), Electrical Overstress (EOS), Electro-migration (EM, an acronym homonym as it turns out, shared by Electromagnetism), Hot Carrier Injection (HCI), Negative Bias Temperature Instability (NBTI), and Operating Voltage DRC (OVD, a hierarchical acronym), to name a few. While this may sound like an exercise to come up with the most esoteric acronym, most of these issues are actually quite familiar to design teams, and some are becoming more critical due to advanced process node effects and design styles. You may be wondering: do I need to worry about circuit reliability issues, and if so, how can I address them?
Legacy process nodes: Do I have to worry about this?
Circuit reliability is not really a new concern; most of the issues described above have been part of our vernacular for 10-20 years. There have been millions of chips taped out on legacy technologies (180nm-40nm) that are successful in their intended production environments. The natural perception is that reliability risks are mostly a problem for the newest process node. Smaller devices, thinner wires and thinner gate oxides are more susceptible to electrical overstress, and each new manufacturing node is more sensitive to specific layout shapes and patterns. The general belief is that designers on the “bleeding” edge have to use the new methods, tools and design techniques, while those working on legacy technologies can continue to be successful with older techniques. However, IC designers at 180nm who assume that circuit reliability is a solved problem may actually be faced with some hidden risks on their next project. Why is that?
As we all know, the key driver of our industry is innovation. Leading edge designers pioneer techniques that are subsequently leveraged by followers who later migrate additional applications to the new node. However, innovation continues at every node, not just the latest. Engineers continue to push performance, functionality, area, and other metrics to deliver improved ROI even on legacy processes. There may be fewer unknowns with an older process, but each new wave of designs targets different applications with different requirements and environmental conditions, and this can introduce new reliability issues.
For example, automotive and medical applications are currently major drivers of new design starts on legacy process technologies. These applications have different environmental factors and different design constraints than the typical consumer applications that employ leading edge processes. Most people will not replace their pacemakers as often as their cell phones (longer life requirement), and no automaker will accept an engine controller device if it is not tested in high temperature conditions. In addition to different stresses and different longevity requirements, there are new circuit functions and topologies that were not present in the first wave of chips at a given node, again due to changing application needs. More analog content, higher voltages (e.g., 50V for automotive), and higher frequencies are just a few of the evolving design requirements that put increased constraints on circuits implemented with more mature process nodes.
Figure 1. A key focus of circuit reliability checking is to prevent damage at the interface between different voltage domains.
With more complex design requirements and more variability in operating environments, the techniques for ensuring circuit reliability also have to change, even for legacy technologies. Higher voltages result in a greater risk of EOS. IC designers need to increase their diligence to ensure that thin-oxide digital transistors are not connected to 50 volt supplies, for example. Designs using high voltages also require increased interconnect spacing, but only in specific locations. If high voltage DRC checks were applied globally, then all spacing checks could be worst case, i.e., assuming that every net would switch between 0 volts to 50 volts. This would lead to extremely conservative designs, excessive die area, higher cost and lower yield.
Many design teams employ user-generated marker layers or text points to check for EOS, but this is an error prone method because it requires the designer to manually determine how voltages propagate throughput the design and manually mark the correct regions for high voltage design rules. Markers are extremely difficult to maintain as the design is changed. Today there are tools that can track the switching potential for every net and every polygon. This information can be leveraged for very precise and efficient OVD checks that use the appropriate spacing constraint based on the actual voltage potentials present for those structures.
Additionally, the more complex nature of designs today creates a risk that well known failure mechanisms, such as ESD, latch-up, and EM, might not be reliably prevented by standard design practices. Today, ensuring a design does not have potential reliability problems requires an integrated verification strategy that combines circuit classification, resistance information, current density calculation and DRC checking.