are some common trends with every new process node that drive
reliability concerns: denser designs, thinner wires, and more devices
incur higher coupling capacitance, higher resistance and additional
design complexity. These effects will, in turn, impact signal integrity
Electro-migration has been a concern for many
generations of ICs. However, FinFET technology, with its combination of
higher drive strengths and implementation at 14/16nm with thinner wires,
presents an additional recipe for circuit failure due to EM. EM
checking using traditional techniques is computationally intensive,
requiring extraction of the parasitic model, simulation and annotation
of the currents on every segment of a design. A typical 16nm/14nm SoC
will have billions of segments and the checking procedure becomes
unacceptably slow. A more practical approach is up-front circuit
classification that identifies nets or segments that will be susceptible
to EM, then applying static and dynamic analysis only to those nets,
rather than using brute force methods.
In addition, transistors
are becoming thinner—they are manufactured with increasingly thin oxide
layers under the gate. The purpose of the oxide is to prevent the
transistor from breaking down under high voltages, and a thinner oxide
means a device is more susceptible to EOS. Today, most ICs have a
multiple-power domain strategy, meaning there are several different Vdds
on the chip. This added complexity makes it extremely difficult to
check for all possible EOS conditions. In fact, a full-chip EOS check
exceeds the capability of today’s standard circuit simulation and
verification methods. Designers need a dedicated tool that provides a
fast and comprehensive analysis of every device and the possible
voltages that will presented to its terminals.
Figure 2. Other circuit checks include DECAP placement, geometry matching and current density checks.
The problems may not be new, but new techniques are needed
the circuit reliability issues discussed above are not new in
themselves, advances in IC design and manufacturing can make them more
complicated, and more difficult to guard against. Traditionally,
designers have used a combination of circuit simulation, design reviews,
design rule checking with marker layers or text points, and other
“home-grown” methodologies to find potential circuit reliability
Due to growing complexity, increased susceptibility,
broader application requirements, and more demanding environmental
conditions, designers need more targeted and sophisticated tools and
techniques to ferret out the sources of electrical failures.
Sophisticated verification will require an integration of circuit,
layout, parasitic and simulation information. Additionally, since many
of these issues are exhibited at block-level and full-chip, efficient
and elegant debugging is required to quickly identify sources of circuit
error. With the emergence of new tools that offer these capabilities,
we now see foundries offering solutions in this area. Reflecting back on
the announcements at DAC, we saw silicon manufacturers at both leading
and mature nodes offering new support and methodologies for circuit
This is just the start of a new segment of EDA, and I
expect there will be a long evolution path as we continue to address
previously “un-checkable” circuit reliability issues with the next
generation of tools. And, with that, of course, we can also expect to
see a few more TLAs.
About the author
is a Director of Product Marketing at Mentor Graphics Corp., overseeing
the marketing activities for Calibre PERC, LVS and extraction products.
He has been with Mentor Graphics for 15 years in various product and
technical marketing roles. Prior to Mentor Graphics, Carey was a design
engineer at Digital Equipment Corp., working on microprocessor design.
Carey holds a BS from Stanford University and an MS from UC Berkeley. He
may be contacted at email@example.com.
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