This is a roundup of news and activities over the past week that may be of interest to people.
Worldwide semiconductor manufacturing equipment spending is projected to total $35.8 billion in 2013, a 5.5 percent decline from 2012 spending of $37.8 billion, according to Gartner, Inc. Gartner said that capital spending will decrease 3.5 percent in 2013, as major producers remain cautious in the face of market weakness. They predict that 2014 semiconductor capital spending will increase 14.2 percent, followed by 10.1 percent growth in 2015. The next cyclical decline will be a mild drop of 3.5 percent in 2016, followed by a return to growth in 2017.
Verifyter AB, a company that I wrote about a year ago in my startup spotlight, have received a round of funding from Spintop Ventures, Sydsvensk Entreprenörfond and EDA veteran Lars-Eric Lundgren. Verifyter has a software tool (PinDown) for the automatic detection and analysis of test failures. They intend to use the funds to expand their sales and support team in the US as well as strengthen the research and development team.
The Accellera Systems Initiative SystemC Verification Working Group has begun a 90-day public review of the SystemC Verification (SCV) Library 2.0, an update to SCV 1.0p2. This release contains an implementation of the verification extensions for Accellera SystemC 2.3.0 and SystemC 2.2.0, and is compatible with the IEEE Standard 1666™: Open SystemC Language. Examples and support for recent compilers is also included. The public review version can be found here after the license agreement is signed.
Mentor Graphics has expanded the Kronos™ Cell Characterization and Analysis platform to include embedded memories. The Kronos platform produces performance models for standard cells, I/Os, complex cells and embedded memories. At 45nm and below, speed and power consumption are much more sensitive to environmental conditions including voltage and noise. Producing accurate models at the appropriate conditions is critical to achieving design success. Algorithms and job distribution reduces characterization time from weeks to days. During characterization, SPICE simulations are continuously monitored, and numerous data checks and recovery mechanisms significantly improve turn-around time.
Synopsys will demonstrate M-PCIe interoperability at the PCI-SIG Developers Conference 2013 between M-PCIe interfaces from Synopsys and Intel using M-PCIe-based switch and endpoint devices. M-PCIe is an engineering change notice (ECN) to the PCI Express (PCIe®) specification and enables designers to leverage their existing knowledge and software investments in PCI Express to reduce the power consumption of their systems-on-chips (SoCs) for low-power applications. Synopsys' M-PCIe solution, which includes silicon-proven DesignWare MIPI M-PHY technology and M-PCIe Controller IP, provides early support for the recently announced M-PCIe specification, enabling designers to accelerate development of their M-PCIe-based designs to hit critical market windows.
In a similar vein, Cadence has announced new design IP for low-power PCI Express (PCIe®) development. The new PCIe IP from Cadence supports x16 configuration, giving designers the maximum performance along with virtualization support to service multi-threaded applications.
MathWorks has announced that Simulink PLC Coder can now generate IEC 61131-3 Structured Text for OMRON programmable logic controllers (PLCs). This advancement allows industrial automation engineering teams to adopt Model-Based Design for manufacturing and power generation equipment controlled by Omron PLCs, including OMRON’s new Sysmac Studio.
Agilent has introduced the U5340A FPGA development kit, powered by a custom Mentor Graphics design engine, for high-speed digitizers. This combines real-time signal processing in the FPGA with Agilent’s on board high-speed digitizers. The FPGA development kit enables original equipment manufacturers and researchers to easily design in high-speed signal acquisition and analysis. The custom Mentor Graphics design engine is embedded in the development kit to support the design, synthesis, simulation and validation of signal-processing algorithms.
Synopsys and United Microelectronics Corporation (UMC) have announced the successful tapeout of UMC's first process qualification vehicle in its 14-nanometer (nm) FinFET process utilizing Synopsys' DesignWare® Logic Library IP portfolio and StarRC™ parasitic extraction solution, a part of the Galaxy™ Implementation Platform. This process qualification vehicle will provide early silicon data, enabling UMC to tune its 14-nm FinFET process and Synopsys to refine its DesignWare IP portfolio for optimal power, performance and area.
UltraSoC has successfully closed a funding round of $2.3million by securing further investment from Octopus Investments bringing the total investment in the business to date to $7.5m. The product, UltraDebug®, is a system-level debug and optimization capability for multiple heterogeneous processor cores including graphics cores and custom accelerators. UltraDebug® is a library of debug IP which will enable detection of software and hardware bugs as well as other important optimization capabilities for memory interfaces and system fabrics.
Tektronix has a series of enhancements to its USB 3.0 test solutions including a transmitter test solution for the SuperSpeedPlus 10 Gb/s specification. Other enhancements include a new USB 3.0 oscilloscope-based layered decode capability and an enhanced automated solution for SuperSpeed USB transmitter testing that improves test throughput by up to 60%.Brian Bailey
– keeping you covered
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