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IP in FPGAs: Blessing and a curse

Dave Orecchio
11/22/2010 03:31 PM EST

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futurewee
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re: IP in FPGAs: Blessing and a curse
futurewee   12/29/2010 1:13:38 PM
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It makes a lot of sense!

Robotics Developer
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re: IP in FPGAs: Blessing and a curse
Robotics Developer   11/24/2010 9:49:23 PM
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Sounds like a great approach to a difficult problem. I worked in the custom ASIC world for 18+ years and would agree that the use of IP is essential to FPGA growth (another part is the performance, gate counts, and feature improvements). There has always been a difference between the simulator model and real hardware (be it a hard macro or a soft macro) that only showed in the final devices whether custom ASICs or FPGAs. The big difference was with FPGAs you had the option to re-code/compile or reroute the device. With ASIC NREs in the 500K to 3million range, simulation, regression testing, emulation were essential and in some cases worked well. There is nothing like tested and proven IP implementations to ease use and increase the probability of success.

dorecchio
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re: IP in FPGAs: Blessing and a curse
dorecchio   11/24/2010 3:58:47 PM
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Hi Sharps_eng, Thank you for posting your comment and the insight you offer. I like your analogy to the impact that microprocessor emulators had on the market, we believe that our solution could do the same or more. Now to answer your questions: 1) Price is approximately the same as the software simulator that we integrate with (Cadence, Mentor and Synopsys) but price varies based on the FPGA we place in the RocketDrive. Our lowest price configuration is $25K. 2) No one has developed a solution like this one. Others have connected hardware to simulators but all of them require you to change your source code to use the hardware. Our CTO and founder Chris Schalick innovated this patent pending solution in a way that it fits seamlessly into your simulation environment and regression environment. An un-moveable requirement as far as I see it. Our customers, like Qualcomm routinely place designs in the RocketDrive untouched by human hands. 3) Simulators have very good hooks into simulators, we have partnerships with Cadence, Mentor and Synopsys and use their tool to test our integration. Our integration with their simulators is so tight that when a user uses our product, they control it completely from the simulator - their native working environment. So I would not call it a hack because of the support from the vendors and our rigorous testing of it. 4) At the beginning of the year, we added a "Soft Patch" capability to RocketVision which enables the user to move blocks in and out of the RocketDrive without rebuilding the FPGA. This innovation cuts the long loops of debug when trying to use FPGAs in system or for ASIC prototypes. It is a very cool and important capability. 5) The interface is our own proprietary high speed interface which is important for any direct integration to a simulator. Again, thank you for your comment and if you are located in the US, have a happy Thanksgiving.

sharps_eng
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re: IP in FPGAs: Blessing and a curse
sharps_eng   11/23/2010 11:43:58 PM
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Gaterocket's website explains their product very well. Next questions: 'How much?' and 'Who else does this kind of stuff?'. They are addressing the inefficient-design-process issues that SoC teams have sleepwalked into, and if it works as neatly as they say, a GateRocket would become an essential tool. Reminds me of the impact made by the first microprocessor emulators to break onto the scene. One other question: I didn't know the RTL simulation software had plug-in hooks that would allow RocketView to map external hardware i/o stimuli into the purely-software simulation application. Anyway, it's a neat hack, as long as it remains supported by the tool vendors. Lastly, what computer I/O does it use? SATA?

Max The Magnificent
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re: IP in FPGAs: Blessing and a curse
Max The Magnificent   11/22/2010 5:12:29 PM
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Thanks for this Dave -- I'm surprised it's taken so long to get FPGA-specific IP topics in the IP-SoC conference ... but it doesn't surprise me that they are there now, and I think that the floodgates will start to open. I also think that there's a good market for small start-ups to develop IP for FPGAs, but as you say the trick is to get everything to work together. Max

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