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Itís unanimous: Debug biggest verification problem

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Alan M. Feldstein
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re: Itís unanimous: Debug biggest verification problem
Alan M. Feldstein   3/6/2011 2:40:33 AM
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So we give the design team more time at the front end of the verification cycle (i.e. create verification plan and develop verification environment) to get organized for debug capability. Because of the increased debug efficiency, this allows us to pull in the back end (i.e. debug HDL and environment) of the schedule, hopefully by more than we pushed out the front. If an immediate ROI is too ambitious, we still know we can create capabilities that are reusable across projects. So we bite the bullet on the first project and get ROI on multiple subsequent projects. If we don't do this, our competitors will.

DrFPGA
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re: Itís unanimous: Debug biggest verification problem
DrFPGA   1/22/2011 4:43:50 PM
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Now if management would just give the design team enough time to add some of these up front techniques to an already tight schedule. Seems like spending money on tools is OK, but providing the time to use them may be difficult to get...

Sean Safarpour
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re: Itís unanimous: Debug biggest verification problem
Sean Safarpour   1/6/2011 4:42:51 PM
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Here are some related links: * MTV workshop: http://www.mtvcon.org/ * Panelist Slides: http://www.vennsa.com/mtv/

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